VLSI Verilog 2014 Projects

VLSI Verilog Projects 2014

  1. 32 Bit×32 Bit Multi precision Razor-Based Dynamic Voltage Scaling Multiplier with Operands Scheduler
  2. A 16-Core Processor With Shared-Memory and
  3. An Optimized Modified Booth Recoder for Efficient
  4. High-Throughput Multistandard Transform
  5. Improved 8-Point Approximate DCT
  6. Area–Delay–Power Efficient Carry-Select Adder
  7. Multifunction Residue Architectures
  8. Area-Delay-Power Efficient Fixed-Point LMS
  9. Aging-Aware Reliable Multiplier Design With
  10. Fast Sign Detection Algorithm for the RNS Module
  11. Efficient Integer DCT Architectures for HEVC
  12. Bit-Level Optimization of Adder-Trees
  13. Design of Efficient Binary Comparators
  14. Reverse Converter Design via Parallel-Prefix Adders
  15. Low-Complexity Low-Latency Architecture for Matching

  VLSI Verilog Projects 2013

  1. Energy-Efficient High-Throughput Montgomery
  2. Error Detection in Majority Logic Decoding of Euclidean
  3. Low-Power, High-Throughput, and Low-Area
  4. Pipelined Radix- Feedforward FFT Architectures
  5. A Single-Channel Architecture for Algebraic
  6. Radix-4 and Radix-8 Booth
  7. High-Performance Hardware
  8. pipelined  Radix 2K Feed forward
  9. Design and Implementation On-Chip Permutation Network for Multiprocessor System-On-Chip
  10. Multioperand Redundant Adders on FPGAs
  11. Global Built-In Self-Repair for 3D Memories with
  12. A Practical NoC Design for Parallel DES Computation
  13. Parallel AES Encryption Engines
  14. VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog
  15. A VLIW architecture for executing multi-scalarvector instructions on unified datapath
  16. A Novel Modulo Adder for
  17. Low-Cost FIR Filter Designs Based on Faithfully
  18. Low-Power, High-Throughput, and Low-Area
  19. Efficient VLSI Architectures of Split-Radix FFT
  20. A Design Technique for Faster Dadda Multiplier
  21. Low-Power, High-Throughput, and Low-Area
  22. BIST Based Test Applications Enhanced with Adaptive Low Power RTPG
  23. Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA
  24. Enhanced Area Efficient Architecture for 128 bit Modified CSLA
  25. High Performance Hardware Implementation
  26. High Performance Pipelined Design for FFT
  27. Implementation of I2C Master Bus Controller
  28. Novel High Speed Vedic Mathematics Multiplier
  29. Period Extension and Randomness Enhancement Using
  30. VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog
  31. VLSI implementation of Fast Addition using
  32. FPGA architecture for OFDM software defined radio with an optimized direct digital frequeney syntherizer
  33. Implementation of UART with BIST Technique in
  34. A High Speed Binary Floating Point Multiplier Using Dadda Algorithm
  35. Soft-Error-Resilient FPGAs Using 2D hamming code
  36. High-Speed Low-Power Viterbi Decoder Design for TCM Decoders
  37. Efficient Majority Logic Fault Detection With
  38. Product code scheney for error correction in mlc nand flash memorles
  39. Scalable Digital CMOS Comparator
  40. Low-Power and Area-Efficient Carry Select Adder
  41. A Nonbinary LDPC Decoder Architecture With Ad
  42. Low-Cost Binary128 Floating-Point FMA Unit
  43. Efficient Majority Logic Fault Detection With
  44. Viterbi-Based Efficient Test Data
  45. Design and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA
  46. Design and FPGA-based Implementation of a High Performance 32-bit DSP Processor
  47. FPGA Implementation of Sine and Cosine Generators using CORDIC Algorithm
  48. Reconfigurable Routers for  low_power_high_performance_routers
  49. Configurable Multimode floating point units
  50. data encoding scheme in noc
  51. A New VLSI Architecture of Parallel Multiplier A
  52. FPGA Implementation of Network on Chip
  53. Design and  Implementation  of  Multi-mode QC­


  1. Can You please send me “aging-aware reliable multiplier design with adaptive hold logic” document and other details to my email id ?

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