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V.L.S.I PROJECTS 2016
 HighSpeed and EnergyEfficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
 Variable Latency Speculative HanCarlson Adder
 An AreaEfficient Relaxed HalfStochastic Decoding Architecture for Nonbinary LDPC Codes
 Reverse Converter Design via ParallelPrefix Adders: Novel Components, Methodology, and Implementations
 Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications
 Design and Analysis of Approximate Compressors for Multiplication
 InputBased Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
 LowPower Programmable PRPG with Test Compression Capabilities
 LowCost HighPerformance VLSI Architecture for Montgomery Modular Multiplication
 Recursive Approach to the Design of a Parallel SelfTimed Adder
 Efficient Coding Schemes for FaultTolerant Parallel Filters
 HighThroughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations
 AgingAware Reliable Multiplier Design With Adaptive Hold Logic
 An AccuracyAdjustment FixedWidth Booth Multiplier Based on Multilevel Conditional Probability
 A Novel AreaEfficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders
 TradeOffs for Threshold Implementations Illustrated on AES
 Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks
 Reliable and Error Detection Architectures of Pomaranch for FalseAlarmSensitive Cryptographic Applications
 A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT
 ResultBiased DistributedArithmeticBased Filter Architectures for Approximately Computing the DWT
 Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes
 Advanced Low Power RISC Processor Design using MIPS Instruction Set
 Scan Test Bandwidth Management for UltralargeScale SystemonChip Architectures
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PROJECT TITLES 
IEEE

1  High – Throughput Finite Field Multipliers Using Redundant Basis For Fpga And Asic Implementations  2015 
2  A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable Orthogonal Approximation Of Dct  2015 
3  Low Delay Single Symbol Error Correction Codes Based On Reed Solomon Codes  2015 
4  Fully Reused VLSI Architecture Of Fm0/Manchester Encoding Using Sols Technique For Dsrc Applications  2015 
5  Obfuscating Dsp Circuits Via HighLevel Transformations  2015 
6  PreEncoded Multipliers Based On NonRedundant Radix4 SignedDigit Encoding  2015 
7  An Efficient Constant Multiplier Architecture Based On VerticalHorizontal Binary Common SubExpression Elimination Algorithm For Reconfigurable Fir Filter Synthesis  2015 
8  Flexible Dsp Accelerator Architecture Exploiting CarrySave Arithmetic  2015 
9  LowLatency HighThroughput Systolic Multipliers Over For Nist Recommended Pentanomials  2015 
10  A Synergetic Use Of Bloom Filters For Error Detection And Correction  2015 
11  Reliable LowPower Multiplier Design Using FixedWidth Replica Redundancy Block  2015 
12  Recursive Approach To The Design Of A Parallel SelfTimed Adder  2015 
13  AgingAware Reliable Multiplier Design With Adaptive Hold Logic  2015 
14  Efficient Sub Quadratic Space Complexity Architectures For Parallel Mpb Single And DoubleMultiplications For All Trinomials Using Toeplitz MatrixVector Product Decomposition  2015 
15  FineGrained Critical Path Analysis And Optimization For AreaTime Efficient Realization Of Multiple Constant Multiplications  2015 
16  Fast Sign Detection Algorithm For The Rns Moduli Set {2n+1 − 1, 2n − 1, 2n}  2015 
17  Algorithm And Architecture For A LowPower ContentAddressable Memory Based On Sparse Clustered Networks  2015 
18  Scan Test Bandwidth Management For UltralargeScale SystemOnChip Architectures  2015 
19  Novel Shared Multiplier Scheduling Scheme For AreaEfficient FFT/IFFT Processors  2015 
20  VLSI Computational Architectures For The Arithmetic Cosine Transform  2015 
21  A Generalization Of Addition Chains And Fast Inversions In Binary Fields  2015 
22  LowPower And AreaEfficient Shift Register Using Pulsed Latches  2015 
23  Communication Optimization Of Iterative Sparse Matrix – Vector Multiply On GPUs And FPGAs  2015 
24  A SelfPowered HighEfficiency Rectifier With Automatic Resetting Of Transducer Capacitance In Piezoelectric Energy Harvesting Systems  2015 
25  LowPower Programmable PRPG With Test Compression Capabilities  2015 
26  One Minimum Only Trellis Decoder For Non – Binary Low – Density Parity – Check Codes  2015 
27  A Low Complexity Scaling Method For The Lanczos Kernel In FixedPoint Arithmetic  2015 
28  Mixing Drivers In ClockTree For Power Supply Noise Reduction  2015 
29  A ClosedLoop Reconfigurable SwitchedCapacitor DCDC Converter For SubmW Energy Harvesting Applications  2015 
30  Simplified Trellis Min–Max Decoder Architecture For Nonbinary LowDensity ParityCheck Codes  2015 
31  New Regular Radix8 Scheme For Elliptic Curve Scalar Multiplication Without PreComputation  2015 
32  Fault Tolerant Parallel Filters Based On Error Correction Codes  2015 
33  Comments On “LowLatency DigitSerial Systolic Double Basis Multiplier Over GF (2^{m} ) Using Subquadrat Ic Toeplitz Matrix Vector Product Approach”  2015 
34  SkewedLoad Test Cubes Based On Functional Broadside Tests For A LowPower Test Set  2015 
35  LowComplexity Tree Architecture For Finding The First Two Minima  2015 
36  Efficient Coding Schemes For FaultTolerant Parallel Filters  2015 
37  PiecewiseFunctional Broadside Tests Based On Reachable States  2015 
38  A Multicycle Test Set Based On A TwoCycle Test Set With Constant Primary Input Vectors  2015 
39  Partially Parallel Encoder Architecture For Long Polar Codes  2015 
40  Novel BlockFormulation And AreaDelay – Efficient Reconfigurable Interpolation Filter Architecture Formulti – Standard SDR Applications  2015 
41  An Optimized Modified Booth Recoder for Efficient Design of the AddMultiply Operator  2014 
42  Data Encoding Techniques for Reducing Energy Consumption in NetworkonChip  2014 
43  A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits  2014 
44  Fast Radix10 Multiplication Using Redundant BCD Codes  2014 
45  A parallel radixsortbased VLSI architecture for finding the first W maximum/minimum values  2014 
46  Multifunction Residue Architectures for Cryptography  2014 
47  AreaDelayPower Efficient FixedPoint LMS Adaptive Filter With Low
AdaptationDelay 
2014 
48  32 Bit×32 Bit Multiprecision RazorBased Dynamic Voltage Scaling Multiplier With Operands Scheduler  2014 
49  Recursive Approach to the Design of a Parallel SelfTimed Adder  2014 
50  Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications  2014 
51  Statistical Analysis of MUXBased Physical Unclonable Functions  2014 
52  LowPower PulseTriggered FlipFlop Design Based on a Signal FeedThrough Scheme  2014 
53  BitLevel Optimization of AdderTrees for Multiple Constant Multiplications for Efficient FIR Filter Implementation  2014 
54  Efficient Integer DCT Architectures for HEVC  2014 
55  CriticalPath Analysis and LowComplexity Implementation of the LMS Adaptive Algorithm  2014 
56  A Method to Extend Orthogonal Latin Square Codes  2014 
57  Efficient FPGA and ASIC Realizations of a DABased Reconfigurable FIR Digital Filter  2014 
58  Analysis and Design of a LowVoltage LowPower DoubleTail Comparator  2014 
59  On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays  2014 
60  Design of Efficient Binary Comparators in QuantumDot Cellular Automata  2014 
61  LowLatency SuccessiveCancellation Polar Decoder Architectures Using 2Bit Decoding  2014 
62  AgingAware Reliable Multiplier Design With Adaptive Hold Logic  2014 
63  LowComplexity LowLatency Architecture for Matching of Data Encoded With Hard Systematic ErrorCorrecting Codes  2014 
64  Area–Delay–Power Efficient CarrySelect Adder  2014 
65  RestorationBased Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences  2014 
66  Scalable Montgomery Modular Multiplication Architecture with LowLatency and LowMemory Bandwidth Requirement  2014 
67  Digitally Controlled Pulse Width Modulator for OnChip Power Management  2014 
68  Input Test Data Volume Reduction for SkewedLoad Tests by Additional Shifting of ScanIn States  2014 
69  AreaDelay Efficient Binary Adders in QCA  2014 
70  Sharing Logic for BuiltIn Generation of Functional Broadside Tests  2014 