MTech VLSI 2015 2016 Live Projects

Find the below 2015-2016 IEEE VLSI Projects List for ME/M.Tech Final Year Students. Here Student can select any project Title., Our VLSI Developers has developed projects as per the journal paper. We can provide Abstract, Project Source Code, Documentation, PPT Presentation and Execution Support. Contact us for more details.

We Provide Journal Projects and solutions for B.Tech, M.Tech and Research, We can provide solution for any paper and develop the code with an extension., If you have selected any paper then Feel free to share your idea with us.

V.L.S.I PROJECTS 2016

  1. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
  2. Variable Latency Speculative Han-Carlson Adder
  3. An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes
  4. Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
  5. Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications
  6. Design and Analysis of Approximate Compressors for Multiplication
  7. Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
  8. Low-Power Programmable PRPG with Test Compression Capabilities
  9. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
  10. Recursive Approach to the Design of a Parallel Self-Timed Adder
  11. Efficient Coding Schemes for Fault-Tolerant Parallel Filters
  12. High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations
  13. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
  14. An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability
  15. A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders
  16. Trade-Offs for Threshold Implementations Illustrated on AES
  17. Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks
  18. Reliable and Error Detection Architectures of Pomaranch for False-AlarmSensitive Cryptographic Applications
  19. A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT
  20. Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT
  21. Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes
  22. Advanced Low Power RISC Processor Design using MIPS Instruction Set
  23. Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures

 

 

S.NO

 

PROJECT TITLES

 

IEEE

 

1 High – Throughput Finite Field Multipliers Using Redundant Basis For Fpga And Asic Implementations 2015
2 A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable Orthogonal Approximation Of   Dct 2015
3 Low Delay Single Symbol Error Correction Codes Based On Reed Solomon Codes 2015
4 Fully Reused VLSI Architecture Of Fm0/Manchester Encoding Using Sols Technique For Dsrc Applications 2015
5 Obfuscating Dsp Circuits Via High-Level Transformations 2015
6 Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit Encoding 2015
7 An Efficient Constant Multiplier Architecture Based On Vertical-Horizontal Binary Common Sub-Expression Elimination Algorithm For Reconfigurable Fir Filter Synthesis 2015
8 Flexible Dsp Accelerator Architecture Exploiting Carry-Save Arithmetic 2015
9 Low-Latency High-Throughput Systolic Multipliers Over For Nist Recommended Pentanomials 2015
10 A Synergetic Use Of Bloom Filters For Error Detection And Correction 2015
11 Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block 2015
12 Recursive Approach To The Design Of A Parallel Self-Timed Adder 2015
13 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic 2015
14 Efficient Sub Quadratic Space Complexity Architectures For Parallel Mpb Single- And Double-Multiplications For All Trinomials Using Toeplitz Matrix-Vector Product Decomposition 2015
15 Fine-Grained Critical Path Analysis And Optimization For Area-Time Efficient Realization Of Multiple Constant Multiplications 2015
16 Fast Sign Detection Algorithm For The Rns Moduli Set {2n+1 − 1, 2n − 1, 2n} 2015
17 Algorithm And Architecture For A Low-Power Content-Addressable Memory Based On Sparse Clustered Networks 2015
18 Scan Test Bandwidth Management For Ultralarge-Scale System-On-Chip Architectures 2015
19 Novel Shared Multiplier Scheduling Scheme For Area-Efficient FFT/IFFT Processors 2015
20 VLSI Computational Architectures For The Arithmetic Cosine Transform 2015
21 A Generalization Of Addition Chains And Fast Inversions In Binary Fields 2015
22 Low-Power And Area-Efficient Shift Register Using Pulsed Latches 2015
23 Communication Optimization Of Iterative Sparse Matrix – Vector Multiply On GPUs And FPGAs 2015
24 A Self-Powered High-Efficiency Rectifier With Automatic Resetting Of Transducer Capacitance In Piezoelectric Energy Harvesting Systems 2015
25 Low-Power Programmable PRPG With Test Compression Capabilities 2015
26 One Minimum Only Trellis Decoder For Non – Binary Low – Density Parity – Check Codes 2015
27 A Low Complexity Scaling Method For The Lanczos Kernel In Fixed-Point Arithmetic 2015
28 Mixing Drivers In Clock-Tree For Power Supply Noise Reduction 2015
29 A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter For Sub-mW Energy Harvesting Applications 2015
30 Simplified Trellis Min–Max Decoder Architecture For Nonbinary Low-Density Parity-Check Codes 2015
31 New Regular Radix-8 Scheme For Elliptic Curve Scalar Multiplication Without Pre-Computation 2015
32 Fault Tolerant Parallel Filters Based On Error Correction Codes 2015
33 Comments On “Low-Latency Digit-Serial Systolic Double Basis Multiplier Over GF (2m ) Using Subquadrat Ic Toeplitz Matrix- Vector Product Approach” 2015
34 Skewed-Load Test Cubes Based On Functional Broadside Tests For A Low-Power Test Set 2015
35 Low-Complexity Tree Architecture For Finding The First Two Minima 2015
36 Efficient Coding Schemes For Fault-Tolerant Parallel Filters 2015
37 Piecewise-Functional Broadside Tests Based On Reachable States 2015
38 A Multicycle Test Set Based On A Two-Cycle Test Set With Constant Primary Input Vectors 2015
39 Partially Parallel Encoder Architecture For Long Polar Codes 2015
40 Novel Block-Formulation And Area-Delay – Efficient Reconfigurable Interpolation Filter Architecture Formulti – Standard SDR Applications 2015
41 An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator 2014
42 Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip 2014
43 A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits 2014
44 Fast Radix-10 Multiplication Using Redundant BCD Codes 2014
45 A parallel radix-sort-based VLSI architecture for finding the first W maximum/minimum values 2014
46 Multifunction Residue Architectures for Cryptography 2014
47 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low

Adaptation-Delay

2014
48 32 Bit×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler 2014
49 Recursive Approach to the Design of a Parallel Self-Timed Adder 2014
50 Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications 2014
51 Statistical Analysis of MUX-Based Physical Unclonable Functions 2014
52 Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme 2014
53 Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation 2014
54 Efficient Integer DCT Architectures for HEVC 2014
55 Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm 2014
56 A Method to Extend Orthogonal Latin Square Codes 2014
57 Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter 2014
58 Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator 2014
59 On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays 2014
60 Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata 2014
61 Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding 2014
62 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic 2014
63 Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes 2014
64 Area–Delay–Power Efficient Carry-Select Adder 2014
65 Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences 2014
66 Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement 2014
67 Digitally Controlled Pulse Width Modulator for On-Chip Power Management 2014
68 Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States 2014
69 Area-Delay Efficient Binary Adders in QCA 2014
70 Sharing Logic for Built-In Generation of Functional Broadside Tests 2014

 

 

VLSI Verilog 2014 Projects

VLSI Verilog Projects 2014

  1. 32 Bit×32 Bit Multi precision Razor-Based Dynamic Voltage Scaling Multiplier with Operands Scheduler
  2. A 16-Core Processor With Shared-Memory and
  3. An Optimized Modified Booth Recoder for Efficient
  4. High-Throughput Multistandard Transform
  5. Improved 8-Point Approximate DCT
  6. Area–Delay–Power Efficient Carry-Select Adder
  7. Multifunction Residue Architectures
  8. Area-Delay-Power Efficient Fixed-Point LMS
  9. Aging-Aware Reliable Multiplier Design With
  10. Fast Sign Detection Algorithm for the RNS Module
  11. Efficient Integer DCT Architectures for HEVC
  12. Bit-Level Optimization of Adder-Trees
  13. Design of Efficient Binary Comparators
  14. Reverse Converter Design via Parallel-Prefix Adders
  15. Low-Complexity Low-Latency Architecture for Matching

  VLSI Verilog Projects 2013

  1. Energy-Efficient High-Throughput Montgomery
  2. Error Detection in Majority Logic Decoding of Euclidean
  3. Low-Power, High-Throughput, and Low-Area
  4. Pipelined Radix- Feedforward FFT Architectures
  5. A Single-Channel Architecture for Algebraic
  6. Radix-4 and Radix-8 Booth
  7. High-Performance Hardware
  8. pipelined  Radix 2K Feed forward
  9. Design and Implementation On-Chip Permutation Network for Multiprocessor System-On-Chip
  10. Multioperand Redundant Adders on FPGAs
  11. Global Built-In Self-Repair for 3D Memories with
  12. A Practical NoC Design for Parallel DES Computation
  13. Parallel AES Encryption Engines
  14. VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog
  15. A VLIW architecture for executing multi-scalarvector instructions on unified datapath
  16. A Novel Modulo Adder for
  17. Low-Cost FIR Filter Designs Based on Faithfully
  18. Low-Power, High-Throughput, and Low-Area
  19. Efficient VLSI Architectures of Split-Radix FFT
  20. A Design Technique for Faster Dadda Multiplier
  21. Low-Power, High-Throughput, and Low-Area
  22. BIST Based Test Applications Enhanced with Adaptive Low Power RTPG
  23. Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA
  24. Enhanced Area Efficient Architecture for 128 bit Modified CSLA
  25. High Performance Hardware Implementation
  26. High Performance Pipelined Design for FFT
  27. Implementation of I2C Master Bus Controller
  28. Novel High Speed Vedic Mathematics Multiplier
  29. Period Extension and Randomness Enhancement Using
  30. VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog
  31. VLSI implementation of Fast Addition using
  32. FPGA architecture for OFDM software defined radio with an optimized direct digital frequeney syntherizer
  33. Implementation of UART with BIST Technique in
  34. A High Speed Binary Floating Point Multiplier Using Dadda Algorithm
  35. Soft-Error-Resilient FPGAs Using 2D hamming code
  36. High-Speed Low-Power Viterbi Decoder Design for TCM Decoders
  37. Efficient Majority Logic Fault Detection With
  38. Product code scheney for error correction in mlc nand flash memorles
  39. Scalable Digital CMOS Comparator
  40. Low-Power and Area-Efficient Carry Select Adder
  41. A Nonbinary LDPC Decoder Architecture With Ad
  42. Low-Cost Binary128 Floating-Point FMA Unit
  43. Efficient Majority Logic Fault Detection With
  44. Viterbi-Based Efficient Test Data
  45. Design and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA
  46. Design and FPGA-based Implementation of a High Performance 32-bit DSP Processor
  47. FPGA Implementation of Sine and Cosine Generators using CORDIC Algorithm
  48. Reconfigurable Routers for  low_power_high_performance_routers
  49. Configurable Multimode floating point units
  50. data encoding scheme in noc
  51. A New VLSI Architecture of Parallel Multiplier A
  52. FPGA Implementation of Network on Chip
  53. Design and  Implementation  of  Multi-mode QC­

MTech VLSI Live Projects

We provide B.Tech & M.Tech VLSI 2014-2015 Academic Projects with projects code, documentation, execution support and explanation.

M. Tech 2014-2015 VLSI Projects

S.No Project Titles YEAR / Month
001 Low-Power and Area-Efficient Carry Select Adder Jan 2014
002 Design of Dedicated Reversible Quantum Circuitry for Square Computation Jan 2014
003 Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing Jan 2014
004 A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter Jan 2014
005 All Optical Reversible Multiplexer Design using Mach-Zehnder Interferometer Jan 2014
006 Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters Jan 2014
007 Designing Hardware-Efficient Fixed-Point FIR Filters in an Expanding Subexpression Space Jan 2014
008 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay Feb 2014
009 Low – Power Digital signal Processor Architecture for wireless sensor Nodes Feb 2014
010 Time-Based All-Digital Technique for Analog Built-in Self-Test Feb 2014
011 Analysis and Design of a Low – voltage Low – Power Double Tail Comparator Feb 2014
012 A new hydrid  multiplier using Dadda and Wallace method Feb 2014
013 Parallel multiplier – accumulator based on radix- 2 modified Booth algorithm by using a VLSI architecture Feb 2014
014 Fully Reused VLSI Architecture of FM0 / Manchester encodingUsing SOLS Technique for DSRC Applications Feb 2014
015 Reverse Converter Design Via Parallel – Prefix Adders: Novel Components, Methodlogy , and Implementations Feb 2014
016 Bit – Level Optimization of Adder – Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation Feb 2014
017 Implementation of floating point MAC Using Residue Number System Feb 2014
018 4-2 Compressor Design with New XOR-XNOR Module Feb 2014
019 Realization of 2:4 reversible decoder and its application Feb 2014
020 Novel Field _Programmable Gate Array Architecture for Computing the  Eigen Value  Decomposition of  Para – Hermitian Polynomial Matrices Mar 2014
021 Data Encoding Techniques for Reducing Energy Consumption  in Network _on _chip Mar 2014
022 Low-Complexity Low-Latency Architecture for Matching of Data Encoded with Hard Systematic Error – Correcting Codes Mar 2014
023 A Synergetic Use of  Bloom Filters For Error Detection and Correction Mar 2014
024 HIGH SPEED VEDIC MULTIPLIER DESIGNSA REVIEW Mar 2014
025 High- Throughput Multi Standard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic Mar 2014
026 Quaternary Logic Lookup  Table in Standard CMOS Mar  2014
027 Universal Set of CMOS Gates for the Synthesis of  Multiple Valued Logic Digital Circuits Mar 2014
028 Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1-1, 2n-1, 2n } Mar 2014
029 Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems Mar 2014
030 VLSI Architecture Design of Guided Filter for 30 Frames/s Full-HD Video Mar 2014
031 Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications Apr 2014
032 A 16-Core Processor With Shared-Memory and Message-Passing Communications Apr 2014
033 32 Bit X 32 Bit  Multiprecision Razor- Based Dynamic Voltage Scaling Multiplier with Operands Scheduler Apr 2014
034 Multifunction Residue Architectures for Cryptography Apr 2014
035 Improved 8 –Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions May 2014
036 Reliable Concurrent Error Detection Architectures for Extended Euclidean –Based Division Over $(rm GF} (2 ^{m})$ May 2014
037 Reconfigurable CORDIC – Based Low – Power DCT Architecture Based on Data Priority May 2014
038 Area – Delay Efficient Binary  Adder in QCA May 2014
039 Low- Complexity Reconfigurable Fast Filter Bank  for Multi –Standard Wireless Recivers May  2014
040 Binary Division algorithm and high Speed Deconvolution algorithm (Based on Ancient Indian Vedic Mathematics) May  2014
041 Design and Implementation of Modified Signed – Digit  Adder May  2014
042 A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix -2 FFT May  2014
043 Radix-2r Arithmetic for Multiplication by a Constant May  2014
044 Design of a Low-Voltage Low –DropOut Regulator June 2014
045 Design and Analysis of Approximate Compressors for Multiplication June 2014
046 Reviewing High –Radix Signed  – Digit Adders June 2014
047 Area – Delay – Power Efficient Carry –Select Adder June 2014
048 Method for designing Multi-Channel RNS Architectures to prevent  Power Analysis SCA June 2014
049 An Optimized Modified Booth Recoder for Efficient Design of the  Add- Multiply Operator July 2014
050 Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS July 2014
051 Precise VLSI Architecture for AI – Based 1-D/2-D Daub -6 Wavelet Filter Bank with Low Adder – Count July 2014
052 A Method to Extend Orthogonal Latin Square Codes July 2014
053 Low – Power Programmable PRPG With Test Compression Capabilities July 2014
054 Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter July 2014
055 Novel Square root algorithm and its FPGA Implementation July 2014
056 High – Throughput Turbo Decoder with Parallel Architecture for LTE Wireless Communication Standards Augu 2014
057 Fast Radix -10 Multiplication Using Redunant BCD Augu2014
058 A parallel radix –sort –based VLSI architecture for finding the first W maximum/minimum values Augu2014
059 Performance Analysis of the  CS-DCSK /BPSK Communication System Sep 2014
060 VLSI Design of a Large – Number  Multiplier for  Fully – Homorphic Encryption Sep 2014

IEEE 2013  & 2012 Projects

S.No Project Titles YEAR
061 High-Speed Low-Power Viterbi Decoder Design for TCM Decoders 2013
062 Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications 2013
063 Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code 2012
064 Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes 2013
065 Multi operand Redundant Adders on FPGAs 2013
066 Data Encoding Schemes in Networks on Chip 2011
067 A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm 2012
068 Design and Implementation of Multi-mode QC-LDPC Decode 2010
069 Data Encoding for Low-Power in Wormhole-Switched Networks-on- Chip 2013
070 Low Complexity Digit Serial Systolic Montgomery Multipliers For Special Class Of GF(2M) 2013
071 Split-path Fused Floating Point Multiply Accumulate (FPMAC). 2013
072 Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. 2013
073 Low Power and Design Reed –Solomon Encoder 2013
074 A Spurious-Power Suppression Technique for Multimedia/DSP Applications (MAC) 2011
075 Digital Filter Implementation Based on the RNS with Diminished-1 Encoded Channel 2012
076 Low Power 64bit Multiplier Design by Vedic Mathematics 2013
077 VLSI implementation of Fast Addition using Quaternary Signed Digit Number System 2013
078 An Efficient High Speed Wallace Tree Multiplier 2013
079 Low Latency Systolic Montgomery Multiplier for finite Field GF (2m) Based on Pentanomials 2013
080 Radix-4 and radix-8 booth encoded multi-modulus multipliers 2013
081 Viterbi Based Efficient Test Data Compression 2013
082 CORDIC Designs for Fixed Angle of Rotation 2013
083 Product codes of MLC NAND  Flash  Memories 2013
084 Pipelined Parallel FFT Architectures via Folding Transformation 2012
085 High Speed Parallel Decimal Multiplication with Redundant Internal Encodings 2013
086 Scalable Digital CMOS Comparator Using a Parallel Prefix Tree 2013
087 Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM). 2013
088 New High-Speed Multioutput Carry Look-Ahead Adders 2013
089 Modulo 2n-2 Arithmetic Units 2013
090 A New RNS based DA Approach fo Inner Product Computation 2013
091 FPGA Architecture for OFDM Software Defined Radio with an optimized Direct Digital Frequency Synthesizer 2013
092 Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA 2013
093 Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems 2013
094 A Single-Channel Architecture for Algebraic Integer Based 8 x 8 2-D DCT Computation 2013
095 Low Power and Design Reed –Solomon Encoder 2013
096 Design Of An On – Chip Permutation  Network For Multiprocessor Soc 2013
097 A Practical NoC Design for Parallel DES Computation 2013
098 Low-Power Logarithmic Number System Addition/Subtraction and their Impact on  Digital Filters 2013
099 Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme 2012
100 Constant Delay Logic 2013
101 Parallel AES Encryption Engines for Many- Core Processor Arrays. 2013
102 Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials 2012
103 VLSI Architecture of Arithmetic code used in SPHIT 2012

We Provide the below:

  • ABSTRACT
  • FULL PROJECT CODE
  • PAPER PUBLISHING ASSISTANCE
  • ROUGH DOCUMENTATION
  • ROUGH PPT

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VLSI Design Concept for Parallel Iterative Algorithms Project Report

Introduction to VLSI Design Concept for Parallel Iterative Algorithms Project:

Designing an circuit becomes more complicated, especially when the Very Large Scale Integration (VLSI) technology node Keeps shrinking down to Nano scale level. Nano-technology allows integration of number of IP macro-cells on a single chip which leads to the development of Dual-core CPU and parallel computing.

A design of parallel iterative algorithm takes to different VLSI technologies in terms of area, power and timing delay. This paper discuss about the efficient strategy for balancing the number of iterations and the computational complexity. In case of having an hardware platform, which requires an iteration step of an iterative algorithm to execute k times, then this situation can be solved by executing the iterative steps in parallel platform. For this we use 

  • Jacobi method – This method computes the EVD of n×n symmetric matrix iteratively by applying a sequence of orthonormal rotations to the left and the right of the matrix.

Architecture Consideration is necessary to simplify the CORDIC architecture. It is possible to implement a full Jacobi EVC array into a single FPGA device. We could only realize a 6×6 multicore array at most in the biggest Xilinx FPGA device, so we must simplify the CORDIC architecture, the first step is modifying a simplified scaling free μ-rotation CORDIC, this simplified PE has 2 adders, 2 shifters and 4 multiplexers, and it reduces the number of inner iterations from 16 or 32 times for a full CORDIC with word length 16 and 32 bits to 6 inner iterations with CORDIC circular rotation mode. 

Experimental results for an cyclic–by–row parallel Jacobi EVD method in Matlab gives an result of

  • Full rotation CORDIC with 32 iteration steps.
  • Half rotation CORDIC with 16 iteration steps.
  • Simplified μ-rotation CORDIC with one single inner iteration step (μ-CORDIC).
  • Simplified μ-rotation CORDIC with 6 inner iteration

FPGA implementation have a modeled μ-rotation CORDIC PE in VHDL and compared with a full-pipeline CORDIC which is generated, experimental results also show that a 25×25 full Jacobi EVD array can be embedded into Xilinx XC5VL330 65nm FPGA device.

Download VLSI Design Concept for Parallel Iterative Algorithms Project Report

2010 Based Vlsi Projects

List of 2010 based vlsi projects:

Electronics and electrical engineering students can find latest 2010 based vlsi projects with project report, paper presentation, source code and reference documents from this site. Students can use this information as reference for their final year projects.

submit  2010 based vlsi projects to us.

Links to download  2010 based vlsi projects: 

  1. Efficient On-Chip Crosstalk Avoidance by Using Codec Design
  2. FPGA implementation of 32-bit CRC Project
  3. Enhancing The Noise Immunity In Dynamic Circuits Project
  4. Implementation of CDMA System Using Gold Code Spread Spectrum
  5. VLSI For Neural Networks And Their Applications Seminar Project

download more related  2010 based vlsi projects.