VLSI Verilog 2014 Projects

VLSI Verilog Projects 2014

  1. 32 Bit×32 Bit Multi precision Razor-Based Dynamic Voltage Scaling Multiplier with Operands Scheduler
  2. A 16-Core Processor With Shared-Memory and
  3. An Optimized Modified Booth Recoder for Efficient
  4. High-Throughput Multistandard Transform
  5. Improved 8-Point Approximate DCT
  6. Area–Delay–Power Efficient Carry-Select Adder
  7. Multifunction Residue Architectures
  8. Area-Delay-Power Efficient Fixed-Point LMS
  9. Aging-Aware Reliable Multiplier Design With
  10. Fast Sign Detection Algorithm for the RNS Module
  11. Efficient Integer DCT Architectures for HEVC
  12. Bit-Level Optimization of Adder-Trees
  13. Design of Efficient Binary Comparators
  14. Reverse Converter Design via Parallel-Prefix Adders
  15. Low-Complexity Low-Latency Architecture for Matching

  VLSI Verilog Projects 2013

  1. Energy-Efficient High-Throughput Montgomery
  2. Error Detection in Majority Logic Decoding of Euclidean
  3. Low-Power, High-Throughput, and Low-Area
  4. Pipelined Radix- Feedforward FFT Architectures
  5. A Single-Channel Architecture for Algebraic
  6. Radix-4 and Radix-8 Booth
  7. High-Performance Hardware
  8. pipelined  Radix 2K Feed forward
  9. Design and Implementation On-Chip Permutation Network for Multiprocessor System-On-Chip
  10. Multioperand Redundant Adders on FPGAs
  11. Global Built-In Self-Repair for 3D Memories with
  12. A Practical NoC Design for Parallel DES Computation
  13. Parallel AES Encryption Engines
  14. VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog
  15. A VLIW architecture for executing multi-scalarvector instructions on unified datapath
  16. A Novel Modulo Adder for
  17. Low-Cost FIR Filter Designs Based on Faithfully
  18. Low-Power, High-Throughput, and Low-Area
  19. Efficient VLSI Architectures of Split-Radix FFT
  20. A Design Technique for Faster Dadda Multiplier
  21. Low-Power, High-Throughput, and Low-Area
  22. BIST Based Test Applications Enhanced with Adaptive Low Power RTPG
  23. Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA
  24. Enhanced Area Efficient Architecture for 128 bit Modified CSLA
  25. High Performance Hardware Implementation
  26. High Performance Pipelined Design for FFT
  27. Implementation of I2C Master Bus Controller
  28. Novel High Speed Vedic Mathematics Multiplier
  29. Period Extension and Randomness Enhancement Using
  30. VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog
  31. VLSI implementation of Fast Addition using
  32. FPGA architecture for OFDM software defined radio with an optimized direct digital frequeney syntherizer
  33. Implementation of UART with BIST Technique in
  34. A High Speed Binary Floating Point Multiplier Using Dadda Algorithm
  35. Soft-Error-Resilient FPGAs Using 2D hamming code
  36. High-Speed Low-Power Viterbi Decoder Design for TCM Decoders
  37. Efficient Majority Logic Fault Detection With
  38. Product code scheney for error correction in mlc nand flash memorles
  39. Scalable Digital CMOS Comparator
  40. Low-Power and Area-Efficient Carry Select Adder
  41. A Nonbinary LDPC Decoder Architecture With Ad
  42. Low-Cost Binary128 Floating-Point FMA Unit
  43. Efficient Majority Logic Fault Detection With
  44. Viterbi-Based Efficient Test Data
  45. Design and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA
  46. Design and FPGA-based Implementation of a High Performance 32-bit DSP Processor
  47. FPGA Implementation of Sine and Cosine Generators using CORDIC Algorithm
  48. Reconfigurable Routers for  low_power_high_performance_routers
  49. Configurable Multimode floating point units
  50. data encoding scheme in noc
  51. A New VLSI Architecture of Parallel Multiplier A
  52. FPGA Implementation of Network on Chip
  53. Design and  Implementation  of  Multi-mode QC­

MTech VLSI Live Projects

We provide B.Tech & M.Tech VLSI 2014-2015 Academic Projects with projects code, documentation, execution support and explanation.

M. Tech 2014-2015 VLSI Projects

S.No Project Titles YEAR / Month
001 Low-Power and Area-Efficient Carry Select Adder Jan 2014
002 Design of Dedicated Reversible Quantum Circuitry for Square Computation Jan 2014
003 Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing Jan 2014
004 A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter Jan 2014
005 All Optical Reversible Multiplexer Design using Mach-Zehnder Interferometer Jan 2014
006 Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters Jan 2014
007 Designing Hardware-Efficient Fixed-Point FIR Filters in an Expanding Subexpression Space Jan 2014
008 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay Feb 2014
009 Low – Power Digital signal Processor Architecture for wireless sensor Nodes Feb 2014
010 Time-Based All-Digital Technique for Analog Built-in Self-Test Feb 2014
011 Analysis and Design of a Low – voltage Low – Power Double Tail Comparator Feb 2014
012 A new hydrid  multiplier using Dadda and Wallace method Feb 2014
013 Parallel multiplier – accumulator based on radix- 2 modified Booth algorithm by using a VLSI architecture Feb 2014
014 Fully Reused VLSI Architecture of FM0 / Manchester encodingUsing SOLS Technique for DSRC Applications Feb 2014
015 Reverse Converter Design Via Parallel – Prefix Adders: Novel Components, Methodlogy , and Implementations Feb 2014
016 Bit – Level Optimization of Adder – Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation Feb 2014
017 Implementation of floating point MAC Using Residue Number System Feb 2014
018 4-2 Compressor Design with New XOR-XNOR Module Feb 2014
019 Realization of 2:4 reversible decoder and its application Feb 2014
020 Novel Field _Programmable Gate Array Architecture for Computing the  Eigen Value  Decomposition of  Para – Hermitian Polynomial Matrices Mar 2014
021 Data Encoding Techniques for Reducing Energy Consumption  in Network _on _chip Mar 2014
022 Low-Complexity Low-Latency Architecture for Matching of Data Encoded with Hard Systematic Error – Correcting Codes Mar 2014
023 A Synergetic Use of  Bloom Filters For Error Detection and Correction Mar 2014
025 High- Throughput Multi Standard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic Mar 2014
026 Quaternary Logic Lookup  Table in Standard CMOS Mar  2014
027 Universal Set of CMOS Gates for the Synthesis of  Multiple Valued Logic Digital Circuits Mar 2014
028 Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1-1, 2n-1, 2n } Mar 2014
029 Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems Mar 2014
030 VLSI Architecture Design of Guided Filter for 30 Frames/s Full-HD Video Mar 2014
031 Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications Apr 2014
032 A 16-Core Processor With Shared-Memory and Message-Passing Communications Apr 2014
033 32 Bit X 32 Bit  Multiprecision Razor- Based Dynamic Voltage Scaling Multiplier with Operands Scheduler Apr 2014
034 Multifunction Residue Architectures for Cryptography Apr 2014
035 Improved 8 –Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions May 2014
036 Reliable Concurrent Error Detection Architectures for Extended Euclidean –Based Division Over $(rm GF} (2 ^{m})$ May 2014
037 Reconfigurable CORDIC – Based Low – Power DCT Architecture Based on Data Priority May 2014
038 Area – Delay Efficient Binary  Adder in QCA May 2014
039 Low- Complexity Reconfigurable Fast Filter Bank  for Multi –Standard Wireless Recivers May  2014
040 Binary Division algorithm and high Speed Deconvolution algorithm (Based on Ancient Indian Vedic Mathematics) May  2014
041 Design and Implementation of Modified Signed – Digit  Adder May  2014
042 A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix -2 FFT May  2014
043 Radix-2r Arithmetic for Multiplication by a Constant May  2014
044 Design of a Low-Voltage Low –DropOut Regulator June 2014
045 Design and Analysis of Approximate Compressors for Multiplication June 2014
046 Reviewing High –Radix Signed  – Digit Adders June 2014
047 Area – Delay – Power Efficient Carry –Select Adder June 2014
048 Method for designing Multi-Channel RNS Architectures to prevent  Power Analysis SCA June 2014
049 An Optimized Modified Booth Recoder for Efficient Design of the  Add- Multiply Operator July 2014
050 Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS July 2014
051 Precise VLSI Architecture for AI – Based 1-D/2-D Daub -6 Wavelet Filter Bank with Low Adder – Count July 2014
052 A Method to Extend Orthogonal Latin Square Codes July 2014
053 Low – Power Programmable PRPG With Test Compression Capabilities July 2014
054 Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter July 2014
055 Novel Square root algorithm and its FPGA Implementation July 2014
056 High – Throughput Turbo Decoder with Parallel Architecture for LTE Wireless Communication Standards Augu 2014
057 Fast Radix -10 Multiplication Using Redunant BCD Augu2014
058 A parallel radix –sort –based VLSI architecture for finding the first W maximum/minimum values Augu2014
059 Performance Analysis of the  CS-DCSK /BPSK Communication System Sep 2014
060 VLSI Design of a Large – Number  Multiplier for  Fully – Homorphic Encryption Sep 2014

IEEE 2013  & 2012 Projects

S.No Project Titles YEAR
061 High-Speed Low-Power Viterbi Decoder Design for TCM Decoders 2013
062 Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications 2013
063 Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code 2012
064 Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes 2013
065 Multi operand Redundant Adders on FPGAs 2013
066 Data Encoding Schemes in Networks on Chip 2011
067 A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm 2012
068 Design and Implementation of Multi-mode QC-LDPC Decode 2010
069 Data Encoding for Low-Power in Wormhole-Switched Networks-on- Chip 2013
070 Low Complexity Digit Serial Systolic Montgomery Multipliers For Special Class Of GF(2M) 2013
071 Split-path Fused Floating Point Multiply Accumulate (FPMAC). 2013
072 Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. 2013
073 Low Power and Design Reed –Solomon Encoder 2013
074 A Spurious-Power Suppression Technique for Multimedia/DSP Applications (MAC) 2011
075 Digital Filter Implementation Based on the RNS with Diminished-1 Encoded Channel 2012
076 Low Power 64bit Multiplier Design by Vedic Mathematics 2013
077 VLSI implementation of Fast Addition using Quaternary Signed Digit Number System 2013
078 An Efficient High Speed Wallace Tree Multiplier 2013
079 Low Latency Systolic Montgomery Multiplier for finite Field GF (2m) Based on Pentanomials 2013
080 Radix-4 and radix-8 booth encoded multi-modulus multipliers 2013
081 Viterbi Based Efficient Test Data Compression 2013
082 CORDIC Designs for Fixed Angle of Rotation 2013
083 Product codes of MLC NAND  Flash  Memories 2013
084 Pipelined Parallel FFT Architectures via Folding Transformation 2012
085 High Speed Parallel Decimal Multiplication with Redundant Internal Encodings 2013
086 Scalable Digital CMOS Comparator Using a Parallel Prefix Tree 2013
087 Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM). 2013
088 New High-Speed Multioutput Carry Look-Ahead Adders 2013
089 Modulo 2n-2 Arithmetic Units 2013
090 A New RNS based DA Approach fo Inner Product Computation 2013
091 FPGA Architecture for OFDM Software Defined Radio with an optimized Direct Digital Frequency Synthesizer 2013
092 Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA 2013
093 Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems 2013
094 A Single-Channel Architecture for Algebraic Integer Based 8 x 8 2-D DCT Computation 2013
095 Low Power and Design Reed –Solomon Encoder 2013
096 Design Of An On – Chip Permutation  Network For Multiprocessor Soc 2013
097 A Practical NoC Design for Parallel DES Computation 2013
098 Low-Power Logarithmic Number System Addition/Subtraction and their Impact on  Digital Filters 2013
099 Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme 2012
100 Constant Delay Logic 2013
101 Parallel AES Encryption Engines for Many- Core Processor Arrays. 2013
102 Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials 2012
103 VLSI Architecture of Arithmetic code used in SPHIT 2012

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VLSI Design Concept for Parallel Iterative Algorithms Project Report

Introduction to VLSI Design Concept for Parallel Iterative Algorithms Project:

Designing an circuit becomes more complicated, especially when the Very Large Scale Integration (VLSI) technology node Keeps shrinking down to Nano scale level. Nano-technology allows integration of number of IP macro-cells on a single chip which leads to the development of Dual-core CPU and parallel computing.

A design of parallel iterative algorithm takes to different VLSI technologies in terms of area, power and timing delay. This paper discuss about the efficient strategy for balancing the number of iterations and the computational complexity. In case of having an hardware platform, which requires an iteration step of an iterative algorithm to execute k times, then this situation can be solved by executing the iterative steps in parallel platform. For this we use 

  • Jacobi method – This method computes the EVD of n×n symmetric matrix iteratively by applying a sequence of orthonormal rotations to the left and the right of the matrix.

Architecture Consideration is necessary to simplify the CORDIC architecture. It is possible to implement a full Jacobi EVC array into a single FPGA device. We could only realize a 6×6 multicore array at most in the biggest Xilinx FPGA device, so we must simplify the CORDIC architecture, the first step is modifying a simplified scaling free μ-rotation CORDIC, this simplified PE has 2 adders, 2 shifters and 4 multiplexers, and it reduces the number of inner iterations from 16 or 32 times for a full CORDIC with word length 16 and 32 bits to 6 inner iterations with CORDIC circular rotation mode. 

Experimental results for an cyclic–by–row parallel Jacobi EVD method in Matlab gives an result of

  • Full rotation CORDIC with 32 iteration steps.
  • Half rotation CORDIC with 16 iteration steps.
  • Simplified μ-rotation CORDIC with one single inner iteration step (μ-CORDIC).
  • Simplified μ-rotation CORDIC with 6 inner iteration

FPGA implementation have a modeled μ-rotation CORDIC PE in VHDL and compared with a full-pipeline CORDIC which is generated, experimental results also show that a 25×25 full Jacobi EVD array can be embedded into Xilinx XC5VL330 65nm FPGA device.

Download VLSI Design Concept for Parallel Iterative Algorithms Project Report

2010 Based Vlsi Projects

List of 2010 based vlsi projects:

Electronics and electrical engineering students can find latest 2010 based vlsi projects with project report, paper presentation, source code and reference documents from this site. Students can use this information as reference for their final year projects.

submit  2010 based vlsi projects to us.

Links to download  2010 based vlsi projects: 

  1. Efficient On-Chip Crosstalk Avoidance by Using Codec Design
  2. FPGA implementation of 32-bit CRC Project
  3. Enhancing The Noise Immunity In Dynamic Circuits Project
  4. Implementation of CDMA System Using Gold Code Spread Spectrum
  5. VLSI For Neural Networks And Their Applications Seminar Project

download more related  2010 based vlsi projects.

Efficient On-Chip Crosstalk Avoidance by Using Codec Design

  • Project Title:    Efficient On-Chip Crosstalk Avoidance by Using Codec Design             

  • Tools Used:   Xilinx Tool.
  • Platform:   VLSI.

 Project Description:   The main objective of developing this Efficient On-Chip Crosstalk Avoidance by Using Codec Design project is to provide crosstalk features. By using this crosstalk we can remove the error code at receiver section. The information transformation between source and destination using storage nodes is the biggest problem now days. The crosstalk code system was implemented by using Fibonacci algorithm. This is one of the best methods to transfer the data without delay & corrupt. This final year ECE project was designed with Xilinx tool under VLSI platform

FPGA implementation of 32-bit CRC Project

  •   Project Title      : FPGA implementation of 32-bit CRC Project
  •   Platform            : VLSI
  •   Language used: VHDL
  •   Software’s used: Modelsim 6.1f, Xilinx ISE 9.2i

  Project Description:

                           FPGA implementation of 32-bit CRC Project deals with error detection in digital data transfer applications. We are going to use CRC for error detection. The Philip Koopman’s polynomial is used for CRC generation, which provides two more bits of error detection capability. In this Electronics & Communication Engineering Project, at the transmitter check bits are appended (codeword) to the data to be transmitted on the network or channel. These check bits are generated by dividing the message polynomial with the generator polynomial. At the receiver section same operation is performed, if the remainder is zero the transmission is error free, otherwise error has been occurred. In this project we are using VHDL for designing the 32- bit CRC. Synthesis, Place & Route are carried out using Xilinx Spartan-3E kit for programming and for verification of the functionality.

Enhancing The Noise Immunity In Dynamic Circuits Project

Project On Noise Immunity Description:

Enhancing The Noise Immunity In Dynamic Circuits projects main idea is to implement a CMOS logic circuit for improving performance in VLSI Chips. At present dynamic CMOS chips are used in designing VLSI chips which are not efficient because of less resistant to nose compare to present new CMOS logic circuit.

         In order to develop a high performance and efficient VLSI Chips there is need to work on reducing noise in dynamic CMOS logic circuit. There are many techniques which are used to solve this problem which work on deep submicron processing technology. In this project we are working on same methods to provide solution for improving reliable operation of VLSI chip.

         This project works on two areas under which noise is generated they are affected power, area occupied and speed. We will implement new method by reducing these factors and implement a new technique. Application is tested with the existing methods and proved to be more efficient compare to other methods.

Implementation of CDMA System Using Gold Code Spread Spectrum

CDMA System Using Gold Code Spectrum Communication Project:

Implementation of CDMA System Using  Gold Code Spread Spectrum is an attempt to implement and compare the CDMA system using gold code algorithms on a Xilinx Spartan-III FPGA. The CDMA transmitter modulates the given input data and spreading, produces the modulated data and gold code as outputs, which demodulates and spreads modulated data to give the given data. This can be observed physically on the FPGA module with the help of the output led’s available. 

Code division Multiple Access mobile technology had become one the widely used mobile communication technology in present wireless communication system. CDMA works on spread spectrum techniques. In this project we use CDMA wireless mobile communication method for changing modulated spread data in to gold code. 


VLSI For Neural Networks And Their Applications Seminar Project

Many students of Electronics and Communication Engineering are exposed to Integrated Circuits (IC’s) on the common stage and including SSI (small scale integration) circuits such as MSI (medium scale integration) or logic gates circuits such as parity encoders or multiplexers.

Neural networks are the modern concept of programming PCs. They are best to the pattern identification and alternate operations are very tough to process with the help of common methods. Programs make use of neural nets and can learn by themselves and accept to modify situations.

The networks might be the upcoming of mathematics. The best method to comprehend is the puzzle which neural networks are utilized to solve. One answer to make the neural network to recognize is C, C++, Java, or Python.

 They include obtained energies and they are able to transfer their personal amount of energy to alternate neurons and this addition includes the particular complex threshold. The human brain is able to learn based on adjusting the power strength of connections. The neurons network produces the great parallel data processing method. It is compared with common computers and the processor is able to process one instructions sequence.

 In pharmacy, Network (NN) has impressed various experts. The easy exploration by Machado (1996) of the PC-based NN formed more than 600 notes. Many uses were examined and determined depending on the design, information of input and output, and the status of results and project. 


VLSI for Neural Networks and Their Applications Seminar Project is concluded that based on simplified account, the man brain includes many ten billion neurons and the neuron is linked to many thousand alternate neurons. Neurons can send and receive different energy quantities. The essential character of neurons is they cannot respond quickly to the power reception.

Download VLSI For Neural Networks And Their Applications Electronics and communication Engineering Final Year Seminar Project.

List of Mat Lab and VLSI projects

The below are the list of Mat Lab and VLSI projects

  1. FPGA based design and implementation of 7-tap folded pipelined fir filter Mat Lab Project
  2. Design and implementation of a soft drink wending machine on fpga. (vhdl)
  3. Design and Implementation of fir filter using verilog hdl on fpga, & analysis using matlab
  4. Design and implementation of a uart VLSI final year project
  5. Design and implementation of eeprom live project
  6. Design and implementation of sloted machine ECE final year project
  7. Design and implementation of pll Mat Lab & VLSI M tech Project
  8. Design and implementation of dct to compress the image
  9. Design and Implementation of a data compress using huffman algorithm using hdl.
  10. Design and implementation of frequency shift keying
  11. Design and implementation of digital to analog converter.
  12. Design and implementation of anti-collision algorithm (slotted alloha algorithm)
  13. Design and implementation of a usb transmitter using hdl
  14. Design and implementation of a usb receiver using hdl
  15. Design of an advance encryption algorithm using hdl
  16. Design of an advance decryption algorithm using hdl
  17. Design and implementation of a rc4 technique Project
  18. Design and analysis of cdma modem using matlab.
  19. Design and implementation and rejection of interference in bluetooth voice transmission.