**VLSI Verilog Projects 2014 **

- 32 Bit×32 Bit Multi precision Razor-Based Dynamic Voltage Scaling Multiplier with Operands Scheduler
- A 16-Core Processor With Shared-Memory and
- An Optimized Modified Booth Recoder for Efficient
- High-Throughput Multistandard Transform
- Improved 8-Point Approximate DCT
- Area–Delay–Power Efficient Carry-Select Adder
- Multifunction Residue Architectures
- Area-Delay-Power Efficient Fixed-Point LMS
- Aging-Aware Reliable Multiplier Design With
- Fast Sign Detection Algorithm for the RNS Module
- Efficient Integer DCT Architectures for HEVC
- Bit-Level Optimization of Adder-Trees
- Design of Efficient Binary Comparators
- Reverse Converter Design via Parallel-Prefix Adders
- Low-Complexity Low-Latency Architecture for Matching

** VLSI Verilog Projects 2013**

- Energy-Efficient High-Throughput Montgomery
- Error Detection in Majority Logic Decoding of Euclidean
- Low-Power, High-Throughput, and Low-Area
- Pipelined Radix- Feedforward FFT Architectures
- A Single-Channel Architecture for Algebraic
- Radix-4 and Radix-8 Booth
- High-Performance Hardware
- pipelined Radix 2K Feed forward
- Design and Implementation On-Chip Permutation Network for Multiprocessor System-On-Chip
- Multioperand Redundant Adders on FPGAs
- Global Built-In Self-Repair for 3D Memories with
- A Practical NoC Design for Parallel DES Computation
- Parallel AES Encryption Engines
- VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog
- A VLIW architecture for executing multi-scalarvector instructions on unified datapath
- A Novel Modulo Adder for
- Low-Cost FIR Filter Designs Based on Faithfully
- Low-Power, High-Throughput, and Low-Area
- Efficient VLSI Architectures of Split-Radix FFT
- A Design Technique for Faster Dadda Multiplier
- Low-Power, High-Throughput, and Low-Area
- BIST Based Test Applications Enhanced with Adaptive Low Power RTPG
- Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA
- Enhanced Area Efficient Architecture for 128 bit Modified CSLA
- High Performance Hardware Implementation
- High Performance Pipelined Design for FFT
- Implementation of I2C Master Bus Controller
- Novel High Speed Vedic Mathematics Multiplier
- Period Extension and Randomness Enhancement Using
- VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog
- VLSI implementation of Fast Addition using
- FPGA architecture for OFDM software defined radio with an optimized direct digital frequeney syntherizer
- Implementation of UART with BIST Technique in
- A High Speed Binary Floating Point Multiplier Using Dadda Algorithm
- Soft-Error-Resilient FPGAs Using 2D hamming code
- High-Speed Low-Power Viterbi Decoder Design for TCM Decoders
- Efficient Majority Logic Fault Detection With
- Product code scheney for error correction in mlc nand flash memorles
- Scalable Digital CMOS Comparator
- Low-Power and Area-Efficient Carry Select Adder
- A Nonbinary LDPC Decoder Architecture With Ad
- Low-Cost Binary128 Floating-Point FMA Unit
- Efficient Majority Logic Fault Detection With
- Viterbi-Based Efficient Test Data
- Design and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA
- Design and FPGA-based Implementation of a High Performance 32-bit DSP Processor
- FPGA Implementation of Sine and Cosine Generators using CORDIC Algorithm
- Reconfigurable Routers for low_power_high_performance_routers
- Configurable Multimode floating point units
- data encoding scheme in noc
- A New VLSI Architecture of Parallel Multiplier A
- FPGA Implementation of Network on Chip
- Design and Implementation of Multi-mode QC