We provide B.Tech & M.Tech VLSI 2014-2015 Academic Projects with projects code, documentation, execution support and explanation.
M. Tech 2014-2015 VLSI Projects
| S.No | Project Titles | YEAR / Month |
| 001 | Low-Power and Area-Efficient Carry Select Adder | Jan 2014 |
| 002 | Design of Dedicated Reversible Quantum Circuitry for Square Computation | Jan 2014 |
| 003 | Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing | Jan 2014 |
| 004 | A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter | Jan 2014 |
| 005 | All Optical Reversible Multiplexer Design using Mach-Zehnder Interferometer | Jan 2014 |
| 006 | Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters | Jan 2014 |
| 007 | Designing Hardware-Efficient Fixed-Point FIR Filters in an Expanding Subexpression Space | Jan 2014 |
| 008 | Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay | Feb 2014 |
| 009 | Low – Power Digital signal Processor Architecture for wireless sensor Nodes | Feb 2014 |
| 010 | Time-Based All-Digital Technique for Analog Built-in Self-Test | Feb 2014 |
| 011 | Analysis and Design of a Low – voltage Low – Power Double Tail Comparator | Feb 2014 |
| 012 | A new hydrid multiplier using Dadda and Wallace method | Feb 2014 |
| 013 | Parallel multiplier – accumulator based on radix- 2 modified Booth algorithm by using a VLSI architecture | Feb 2014 |
| 014 | Fully Reused VLSI Architecture of FM0 / Manchester encodingUsing SOLS Technique for DSRC Applications | Feb 2014 |
| 015 | Reverse Converter Design Via Parallel – Prefix Adders: Novel Components, Methodlogy , and Implementations | Feb 2014 |
| 016 | Bit – Level Optimization of Adder – Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation | Feb 2014 |
| 017 | Implementation of floating point MAC Using Residue Number System | Feb 2014 |
| 018 | 4-2 Compressor Design with New XOR-XNOR Module | Feb 2014 |
| 019 | Realization of 2:4 reversible decoder and its application | Feb 2014 |
| 020 | Novel Field _Programmable Gate Array Architecture for Computing the Eigen Value Decomposition of Para – Hermitian Polynomial Matrices | Mar 2014 |
| 021 | Data Encoding Techniques for Reducing Energy Consumption in Network _on _chip | Mar 2014 |
| 022 | Low-Complexity Low-Latency Architecture for Matching of Data Encoded with Hard Systematic Error – Correcting Codes | Mar 2014 |
| 023 | A Synergetic Use of Bloom Filters For Error Detection and Correction | Mar 2014 |
| 024 | HIGH SPEED VEDIC MULTIPLIER DESIGNSA REVIEW | Mar 2014 |
| 025 | High- Throughput Multi Standard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic | Mar 2014 |
| 026 | Quaternary Logic Lookup Table in Standard CMOS | Mar 2014 |
| 027 | Universal Set of CMOS Gates for the Synthesis of Multiple Valued Logic Digital Circuits | Mar 2014 |
| 028 | Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1-1, 2n-1, 2n } | Mar 2014 |
| 029 | Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems | Mar 2014 |
| 030 | VLSI Architecture Design of Guided Filter for 30 Frames/s Full-HD Video | Mar 2014 |
| 031 | Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications | Apr 2014 |
| 032 | A 16-Core Processor With Shared-Memory and Message-Passing Communications | Apr 2014 |
| 033 | 32 Bit X 32 Bit Multiprecision Razor- Based Dynamic Voltage Scaling Multiplier with Operands Scheduler | Apr 2014 |
| 034 | Multifunction Residue Architectures for Cryptography | Apr 2014 |
| 035 | Improved 8 –Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions | May 2014 |
| 036 | Reliable Concurrent Error Detection Architectures for Extended Euclidean –Based Division Over $(rm GF} (2 ^{m})$ | May 2014 |
| 037 | Reconfigurable CORDIC – Based Low – Power DCT Architecture Based on Data Priority | May 2014 |
| 038 | Area – Delay Efficient Binary Adder in QCA | May 2014 |
| 039 | Low- Complexity Reconfigurable Fast Filter Bank for Multi –Standard Wireless Recivers | May 2014 |
| 040 | Binary Division algorithm and high Speed Deconvolution algorithm (Based on Ancient Indian Vedic Mathematics) | May 2014 |
| 041 | Design and Implementation of Modified Signed – Digit Adder | May 2014 |
| 042 | A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix -2 FFT | May 2014 |
| 043 | Radix-2r Arithmetic for Multiplication by a Constant | May 2014 |
| 044 | Design of a Low-Voltage Low –DropOut Regulator | June 2014 |
| 045 | Design and Analysis of Approximate Compressors for Multiplication | June 2014 |
| 046 | Reviewing High –Radix Signed – Digit Adders | June 2014 |
| 047 | Area – Delay – Power Efficient Carry –Select Adder | June 2014 |
| 048 | Method for designing Multi-Channel RNS Architectures to prevent Power Analysis SCA | June 2014 |
| 049 | An Optimized Modified Booth Recoder for Efficient Design of the Add- Multiply Operator | July 2014 |
| 050 | Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS | July 2014 |
| 051 | Precise VLSI Architecture for AI – Based 1-D/2-D Daub -6 Wavelet Filter Bank with Low Adder – Count | July 2014 |
| 052 | A Method to Extend Orthogonal Latin Square Codes | July 2014 |
| 053 | Low – Power Programmable PRPG With Test Compression Capabilities | July 2014 |
| 054 | Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter | July 2014 |
| 055 | Novel Square root algorithm and its FPGA Implementation | July 2014 |
| 056 | High – Throughput Turbo Decoder with Parallel Architecture for LTE Wireless Communication Standards | Augu 2014 |
| 057 | Fast Radix -10 Multiplication Using Redunant BCD | Augu2014 |
| 058 | A parallel radix –sort –based VLSI architecture for finding the first W maximum/minimum values | Augu2014 |
| 059 | Performance Analysis of the CS-DCSK /BPSK Communication System | Sep 2014 |
| 060 | VLSI Design of a Large – Number Multiplier for Fully – Homorphic Encryption | Sep 2014 |
IEEE 2013 & 2012 Projects
| S.No | Project Titles | YEAR |
| 061 | High-Speed Low-Power Viterbi Decoder Design for TCM Decoders | 2013 |
| 062 | Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications | 2013 |
| 063 | Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code | 2012 |
| 064 | Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes | 2013 |
| 065 | Multi operand Redundant Adders on FPGAs | 2013 |
| 066 | Data Encoding Schemes in Networks on Chip | 2011 |
| 067 | A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm | 2012 |
| 068 | Design and Implementation of Multi-mode QC-LDPC Decode | 2010 |
| 069 | Data Encoding for Low-Power in Wormhole-Switched Networks-on- Chip | 2013 |
| 070 | Low Complexity Digit Serial Systolic Montgomery Multipliers For Special Class Of GF(2M) | 2013 |
| 071 | Split-path Fused Floating Point Multiply Accumulate (FPMAC). | 2013 |
| 072 | Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. | 2013 |
| 073 | Low Power and Design Reed –Solomon Encoder | 2013 |
| 074 | A Spurious-Power Suppression Technique for Multimedia/DSP Applications (MAC) | 2011 |
| 075 | Digital Filter Implementation Based on the RNS with Diminished-1 Encoded Channel | 2012 |
| 076 | Low Power 64bit Multiplier Design by Vedic Mathematics | 2013 |
| 077 | VLSI implementation of Fast Addition using Quaternary Signed Digit Number System | 2013 |
| 078 | An Efficient High Speed Wallace Tree Multiplier | 2013 |
| 079 | Low Latency Systolic Montgomery Multiplier for finite Field GF (2m) Based on Pentanomials | 2013 |
| 080 | Radix-4 and radix-8 booth encoded multi-modulus multipliers | 2013 |
| 081 | Viterbi Based Efficient Test Data Compression | 2013 |
| 082 | CORDIC Designs for Fixed Angle of Rotation | 2013 |
| 083 | Product codes of MLC NAND Flash Memories | 2013 |
| 084 | Pipelined Parallel FFT Architectures via Folding Transformation | 2012 |
| 085 | High Speed Parallel Decimal Multiplication with Redundant Internal Encodings | 2013 |
| 086 | Scalable Digital CMOS Comparator Using a Parallel Prefix Tree | 2013 |
| 087 | Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM). | 2013 |
| 088 | New High-Speed Multioutput Carry Look-Ahead Adders | 2013 |
| 089 | Modulo 2n-2 Arithmetic Units | 2013 |
| 090 | A New RNS based DA Approach fo Inner Product Computation | 2013 |
| 091 | FPGA Architecture for OFDM Software Defined Radio with an optimized Direct Digital Frequency Synthesizer | 2013 |
| 092 | Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA | 2013 |
| 093 | Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems | 2013 |
| 094 | A Single-Channel Architecture for Algebraic Integer Based 8 x 8 2-D DCT Computation | 2013 |
| 095 | Low Power and Design Reed –Solomon Encoder | 2013 |
| 096 | Design Of An On – Chip Permutation Network For Multiprocessor Soc | 2013 |
| 097 | A Practical NoC Design for Parallel DES Computation | 2013 |
| 098 | Low-Power Logarithmic Number System Addition/Subtraction and their Impact on Digital Filters | 2013 |
| 099 | Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme | 2012 |
| 100 | Constant Delay Logic | 2013 |
| 101 | Parallel AES Encryption Engines for Many- Core Processor Arrays. | 2013 |
| 102 | Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials | 2012 |
| 103 | VLSI Architecture of Arithmetic code used in SPHIT | 2012 |
We Provide the below:
- ABSTRACT
- FULL PROJECT CODE
- PAPER PUBLISHING ASSISTANCE
- ROUGH DOCUMENTATION
- ROUGH PPT
Contact us for more details.
Time-Based All-Digital Technique for Analog Built-in Self-Test
BASIC PAPER
ABSTRACT
FULL PROJECT CODE
PAPER PUBLISHING ASSISTANCE
ROUGH DOCUMENTATION
ROUGH PPT
Sir i need all the information about this project including ppt.
“FPGA Architecture for OFDM Software Defined Radio with an optimized Direct Digital Frequency Synthesizer”
please send me the details as soon as possible.
Could you provide all the details on Low power carry select adder
Binary Division algorithm and high Speed Deconvolution algorithm (Based on Ancient Indian Vedic Mathematics)
Time-Based All-Digital Technique for Analog Built-in Self-Test
BASIC PAPER
ABSTRACT
FULL PROJECT CODE
PAPER PUBLISHING ASSISTANCE
ROUGH DOCUMENTATION
ROUGH PPT
Plz send me the
BASIC PAPER
ABSTRACT
FULL PROJECT CODE
PAPER PUBLISHING ASSISTANCE
ROUGH DOCUMENTATION
ROUGH PPT
on Low- Complexity Reconfigurable Fast Filter Bank for Multi –Standard Wireless Recivers Project as soon as possible.
sir i need all the information for” Fast Radix -10 Multiplication Using Redunant BCD” include ppt..so please send to my mail..
Sir
i want a some document and code for “Vehicle licence plate detection/ Extraction from image”.
“Fully Reused VLSI Architecture of FM0 / Manchester encodingUsing SOLS Technique for DSRC Applications”
plz send the rough documentation of this project
Plz send me the
BASIC PAPER
ABSTRACT
FULL PROJECT CODE
PAPER PUBLISHING ASSISTANCE
ROUGH DOCUMENTATION
ROUGH PPT
on Time-Based All-Digital Technique for Analog Built-in Self-Test.
Plz send me the
BASIC PAPER
ABSTRACT
FULL PROJECT CODE
PAPER PUBLISHING ASSISTANCE
ROUGH DOCUMENTATION
ROUGH PPT
on Data Encoding Techniques for Reducing Energy Consumption in Network _on _chip
Sir i need all the information about the Time-Based All-Digital Technique for Analog Built-in Self-Test.
Please send me the
BASIC PAPER
ABSTRACT
FULL PROJECT CODE
PAPER PUBLISHING ASSISTANCE
ROUGH DOCUMENTATION
ROUGH PPT
Fast Radix -10 Multiplication Using Redunant BCD . please send me abstract of this project.
could you send all details as on
” multi operand redundant adders on fpgas”
please send as early as possible….
sir.. plz send me full details of multi precison adders in vlsi
sir,could you please provide the full details of weather monitoring system
good morning sir, please. send base paper,abtract,full project code ,paper publishing asistance for projects. 1 area delay power delay efficient carry select adder 2.core processor with shared memory and message passing communication 3.analysis and design of a low voltage low power double tail comparator 4.low power digital signal processor architecture for wirless sensor nodes 5. low power and area efficient carry select adder thank you sir.