Project On Noise Immunity Description:

Enhancing The Noise Immunity In Dynamic Circuits projects main idea is to implement a CMOS logic circuit for improving performance in VLSI Chips. At present dynamic CMOS chips are used in designing VLSI chips which are not efficient because of less resistant to nose compare to present new CMOS logic circuit.

         In order to develop a high performance and efficient VLSI Chips there is need to work on reducing noise in dynamic CMOS logic circuit. There are many techniques which are used to solve this problem which work on deep submicron processing technology. In this project we are working on same methods to provide solution for improving reliable operation of VLSI chip.

         This project works on two areas under which noise is generated they are affected power, area occupied and speed. We will implement new method by reducing these factors and implement a new technique. Application is tested with the existing methods and proved to be more efficient compare to other methods.