Introduction to Efficient Encryption Decryption and Compact Module for FPGA Implementation :

This paper suggested solutions for effective and compact FGA implementation of the AES.  Also discussed on how to provide a low-cost solution to manage with the sub keys computed during the decryption and efficient usage of the key schedule, data path parts. 


NIST selected Rijndael as the new Advanced Encryption Standard to replace the old Data Encryption Standard (DES). DES implementation reaches higher throughput when compared to that of AES implementation. But speed efficient designs of DES are not always relevant solutions. Also many applications needs smaller throughput.  Only the 128 bit encryption version is considered as part of AES algorithm, where the 128-bit data block is called state and its key called as RoundKey, with 4 rows and columns respectively.  The AES round provides multiple opportunities of parallelism. The round in AES design is consists of 16 S-boxes and four 32-bit MixColumn operations, which works on independent data.

One of the drawbacks of AES is that the AddRoundKey is executed after MixColumn during encryption and before InvMixColumn during decryption. Such encryption/decryption implementation requires additional switching logic in order to select appropriate data paths, which can affect the time performance.  In advance, both RoundKeys and InvRoundKey will compute and store on one RAM block, based on which the implementation of AES key schedule takes place.  Data path and key schedule parts combined together to give final AES design.  To calculate a new complete InvRoundeys AES design need to do 92 cycles, in the worst case. 


If the use of three internal RAM blocks is not considered then AES is more effective. Among the 3-DES, AES is more efficient. The proposed solution by this paper is of low cost and perfectly suits to cryptographic embedded applications.  AES design implementation based on one complete round, until the entire encryption or decryption is achieved the data will iteratively loop through this round.

Download  Efficient Encryption Decryption and Compact Module for FPGA Implementation.