ECE Seminar Topic and Report on VHDL

Introduction to Seminar Topic on VHDL:

Central electronics engineering research institute was started in the year 1953, and is designing various products required for the electronic industry needs. The CEERI is been undertaking the research and development in the areas of electronic systems and semiconductors and microwave tubes area.

All these design patterns come under VLSI and we program the devices using VHDL process.. In this paper we will see how electronic components are designed using the VHDL process. We will also look into the switching theory and logic design used for designing the combinational circuits.

Brief into VHDL:

VHDL is a verilog hardware description language used for programming the electronic systems. It is used for modeling digital systems and is similar to the programming language like C++. A synthesizer is used in VHDL for converting the source code to hardware description language the code which gets implemented in the circuit. To write a VHDL program we should design a circuit manually and there types of approaches for writing the code.

To describe the hardware modules we will use an entity in VHDL. By using the entity declaration we will declare the user interface function and by using the architecture we will know about the elements present in the design. We have data flow modeling and behavioral and structuring models by which we write the code. For storing the present and the past inputs we will use the sequential or combinational circuits required for the design.


Thus we can conclude that verilog hardware description language is the most efficient programming method for designing the electronic systems. To design a robust code we can use any of the required data flow or the structural or the behavioral styles for writing the code.

Leave a Reply

Your email address will not be published. Required fields are marked *