Introduction to Seminar Topic on Smart Memories :
The smart memories are also known as modular computers. The smart memory contains array of processors and one-dieDRAMconnected by the packet based dynamically connected routed network. The network connects high speed pins to connect with multiple chips. The initial hardware design contains processor tile design and aspects. The processor tile is compromise between the VLSI wire constraints and computational efficiency.
The processor tiles have processor equal to the MIPSR5000 with 64KB on-die Cache. This contains 2-4MB DRAM depending on the cell size. The 400mm2 die can hold 64 processor tiles and some DRAM tiles. By combining the four tiles a Quad processing tile is formed by internet working between them which are used for computational complexity functions. The number hops between the tiles is decreased by forming global network. Compared to today most of the processors have multi-functional segments depending on number of precessions.
The smart memories contain re-configurable memory system. Cross-Bar internetwork connection, Along with processor core and quad band network. For the purpose of balancing the computation, communication and storage the processor tile is allocated equally.
The memory system contains 16 8kb SRAMS. Actually SRAMS are made out of small bock sizes. Larger SRAMS are made out by connecting many Smaller SRAMS. The total memory is 128KB per tile. The logical array memory is 1024x64b which is capable of reading writing modifying.
The processing was 64-bit processing engine with re-configurable memory/decode. The each integer cluster contains ALU register files load/store unit. The floating point cluster needs high bandwidth for sustain parallel issue operations. The LRF structure provides efficient bandwidth as required. The floating point register provides a central register pool of LRF. For the optimal utilization of resources instruction bandwidth is to be tailored to the application needs. The smart memory path can be sup-port wide or narrow instruction .
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