A Low Power Digital Based Reconfigurable FIR Filter

The main aim & objective of this A Low Power Digital Based Re configurable FIR Filter & A Low Power Multiplier-Less FFT Processor Architecture project is to develop digit-re-configurable finite impulse response (FIR) filter technology. This Mat Lab project application gives a secure, flexible and low-power consuming system to finite impulse response filters with a vast range of tap width & length. In this system an 8-digit re configurable finite impulse response filter circuit chip is implemented on  field-programmable gate array.

The complete design of this VLSI final year project is going to be implemented using hardware description language, using functional simulation will be performed, then the design will be synthesized using Xilinx-ISE, then the bit file will be generated and programmed on to field-programmable gate array (FPGA).

For more information about this  A Low Power Digital Based Reconfigurable FIR Filter & A Low Power Multiplier-Less FFT Processor Architecture MATLAB  Live Project contact us.

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7 Replies to “A Low Power Digital Based Reconfigurable FIR Filter”

  1. please can you help with a full version of “A Low Power Digital Based Reconfigurable FIR Filter” i wants to use it as my final year project topic. we are asked to use MATLab in our project and I don’t have it knowledge. Please sir I need desperately need your assistance and guidance.
    Even if it is another topic I will welcome it thank you sir.Here is my email:muhammadabatcha@yahoo.com or muhammadabatcha11@gmail.com

  2. sir
    pl send me the code and report for this didital fir filter. i want to use it for my final project.
    thanks a lot

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