The main aim & objective of this A Low Power Digital Based Re configurable FIR Filter & A Low Power Multiplier-Less FFT Processor Architecture project is to develop digit-re-configurable finite impulse response (FIR) filter technology. This Mat Lab project application gives a secure, flexible and low-power consuming system to finite impulse response filters with a vast range of tap width & length. In this system an 8-digit re configurable finite impulse response filter circuit chip is implemented on field-programmable gate array.
The complete design of this VLSI final year project is going to be implemented using hardware description language, using functional simulation will be performed, then the design will be synthesized using Xilinx-ISE, then the bit file will be generated and programmed on to field-programmable gate array (FPGA).
For more information about this A Low Power Digital Based Reconfigurable FIR Filter & A Low Power Multiplier-Less FFT Processor Architecture MATLAB Live Project contact
‹‹‹ Design and Implementation of a Full Custom of a Full Adder & Subtractor MAT LAB project