Projects for Electronics High Speed Low Power Multiplier with the Spurious Power Suppression depicts the application of an advanced edition of Spurious Power Suppression Technique (SPST) on either high speed multipliers with low power consumption. In this technique, when we come across a part of data that has no effect in the final results computed then the circuit of the SPST responsible for data controlling latches this part so as to prevent unnecessary data transmissions in the mathematical units. This means that spurious data signals are removed through filtering. To perform multiplication, a modified form of Booth Algorithm is used.
This Topic makes use of a detection logic circuit which is used to identify the useful range of data of arithmetic units i.e. adders or multipliers. This method implements the concept of dividing the arithmetic units into Most significant part (MSP) and Least Significant Part (LSP). It then disregards those MSP parts which have no effect on the result and hence only using those bits which are computed in the final result.
There are two methods to filter out the unnecessary switching power. One way is through registers and the other is through AND gates. On scrutiny through simulation of SPST realization through AND gates shows that this combination possesses high flexibility in terms of regulating the data assertion time. This leads to a marked increase in speed and reduction in power.
Thus, Projects for Electronics High Speed Low Power Multiplier with the Spurious Power Suppression is designed. The multiplier in this project is devised by furnishing SPST on a Booth encoder amended for this purpose. This encoder will lessen the number of partial products. The Spurious Power Suppression technique eliminates unnecessary addition and thereby reduces the switching power dissipation. The design of this project is established by making use of Xilinx 9.1 utilizing Verilog HDL coding.
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