Design Verification and Synthesis of Floating Point Arithmetic Unit

Design Verification and Synthesis of Floating Point Arithmetic Unit: An arithmetic-logic unit (ALU) carries out arithmetic and logic operations on the operands instructed by the computer. ALU is the part of computer and is divided into two units as an arithmetic unit (AU) and a logic unit (LU). Few processors have one or more number of AU like one is for fixed-point operations and another for floating-point operations.

Arithmetic operations such as addition, subtraction, multiplication and division are performed by arithmetic and logic unit (ALU) performs. It also performs logical operations such as AND, OR, shift left and shift right etc.

A floating-point unit (FPU) is also a part of a computer system which carries out operations on floating point numbers. The typical operations are addition, subtraction, multiplication, and division.

Integer arithmetic performs operations on integers. It takes integers as an input and also gives integer as an output and the operations of integer arithmetic such as addition, subtraction, multiplication, division, logical operations and shifting.

Adders are implemented by taking multiple copies of simple components and the components are half adders and full adders. Division is implemented in the form of formula as Dividend=(divisor * quotient) + remainder. A simple floating point number (N) uses a fraction (F), base (B), and exponent (E) which is expressed as N=F * BE. Logic synthesis is the method of converting a high-level description into an optimized gate-level presentation and given by standard cell library and certain design constraints.


The floating point arithmetic unit contains floating point adder, floating point subtractor, floating point multiplier, floating point divider thoroughly verified by the test bench module. Using RTL Cadence Synthesis Tools, more information is provided about cells, power, timing analysis for performing floating point operations. With the help of design of arithmetic unit, we can implement low power consuming floating point and high speed processors and also parameterized modules can be implemented for floating point arithmetic unit.

Download Design Verification and Synthesis of Floating Point Arithmetic Unit ECE & EEE B Tech/ BE Final Project Report and Document.

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