Design And Implementation Of 64 Bit ALU Using VHDL

Design And Implementation Of 64 Bit ALU Using VHDL: VHDL is standard language of an industry for the modeling, description, and synthesis of digital circuits and systems. It extends as Very High Speed Integrated Circuits (VHISC) program. It needs standard language for describing the structure and function of integrated circuits (IC).

VHDL is suited with programmable logic devices for designing. Now engineers can quickly and efficiently accomplish a design with the help of large capacity CPLDs and FPGAs of 500 to 100,000 gates. This language is a high level language to describe large circuits to market rapidly.

VHDL gives support to creation of libraries to store components for reuse in particular designs. It provides probability of code between synthesis and simulation tools. It is a device of independent design. It also converts a design from a programmable logic to an ASIC implementation.

VHDL enables logarithmic register transfer and logic gate level. With the help of VHDL, a user is able to abstract implementation details of a design. VHDL provides mixed level design described in a high level of abstraction and also in a lower level of abstraction. The mixed level simulation focuses on the design of the timing critical modules.

VHDL describes a model for a digital hardware device. It specifies the external and internal views of the device. The building blocks of VHDL language are Entity, Architecture, Package, and Process. There are different modelling styles such as dataflow style of modelling, structural style of modelling, and behavioral style of modeling etc.

Design And Implementation Of 64 Bit ALU Using VHDL Conclusion:

Behavioural modelling and structural modelling provide the implementation of 64 bit ALU. The design of an ALU includes logical operations which are implemented with simple gates to operate independently. The mathematical operations of ALU are performed using repeated additions. Multiplication and division are designed as a single unit along with other operations of ALU. The design has three modules and outputs are combined at the top most level using a multiplexer.

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