ABSTRACT:The objective of FPGA Based Implementation Of 7-Tap Folded Pipelined Fir Filter is to develop real time, reliable and fast digital signal processing systems which can be achieved through hardware implementations. In this project a new design is proposed i.e, FPGA based implementation of a folded pipelined 7-tap Finite-impulse response (FIR).
The design of 7-tap folded finite-impulse response (FIR) filter based on pipelined multiplier arrays is considered. Multiplier arrays have canonic structure and can achieve high throughput since they can be pipelined at the bit-level.. The carry–save multiplier array is examined. In order to achieve further hardware reduction the intermediate results are handled directly in bit-skew form, in which they are produced by the arrays.
Implementation strategy for 7-tap the FIR filters includes the Verilog HDL code for each block is written in a synthesizable way. Test benches are written for each module and are simulated in Xilinx Sim environment. After satisfactory functioning of each block, these blocks are combined to form the filter. This filter block is then tested by generating appropriate test vectors through test bench.
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