FPGA implementation of 32-bit CRC Project

  •   Project Title      : FPGA implementation of 32-bit CRC Project
  •   Platform            : VLSI
  •   Language used: VHDL
  •   Software’s used: Modelsim 6.1f, Xilinx ISE 9.2i

  Project Description:

                           FPGA implementation of 32-bit CRC Project deals with error detection in digital data transfer applications. We are going to use CRC for error detection. The Philip Koopman’s polynomial is used for CRC generation, which provides two more bits of error detection capability. In this Electronics & Communication Engineering Project, at the transmitter check bits are appended (codeword) to the data to be transmitted on the network or channel. These check bits are generated by dividing the message polynomial with the generator polynomial. At the receiver section same operation is performed, if the remainder is zero the transmission is error free, otherwise error has been occurred. In this project we are using VHDL for designing the 32- bit CRC. Synthesis, Place & Route are carried out using Xilinx Spartan-3E kit for programming and for verification of the functionality.

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