Design Of 7 TAP FIR Filter Using HDL And Analysis Using MATLAB project explains about a new design of FIR filter to determine control circuits in DSP architectures.  This project can be useful in DSP architecture where different operations using algorithms are time multiplexed in to single functional unit. In order to reduce space in the circuit we need to use multiplexing in algorithms so here in order to reduce space we are running total functional units in a single execution.

In order to check the result of the system Xilinx’s software is used as simulator which is used for simulating VHDL codes.  Inputs given to this simulator are co-efficient of the FIR filter generated by MATLAB.

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