Introduction to An Efficient Architecture for 2-D Lifting-based discrete Wavelet Transform Presentation:
This CSE PPT topic is about an efficient VLSI architecture for implementing the 2-D discrete wavelet transform. The number of applications based on integrated circuits resulted in high performance computing, telecommunications, and consumer electronics has been increasing. In this paper we discuss about VLSI, the whole architecture is designed in such a way that there is an increase in the speed and also the utilization of hardware is done efficiently.
One of the most important characteristics of for today’s services focusses on the higher bandwidth and also high processing power. The other characteristic which is focussed more is the personalized services to the user depending on the user requirement which includes the flexibility also the mobility feature.
When we consider VLSI design styles, several design styles can be considered for chip implementation of specified algorithms. Each design style has its own advantages as well as disadvantages and thus an appropriate choice has to be made by designers in order to provide the functionality at low cost. It includes Field Programmable Gate Array an array of logic cells connected via routing channels. These cells include Special I/O cells and logic cells. When we consider that other design style which comes after FPGA is Gate Array, which is capable of processing fast. The implementation includes with the metal mask design and also processing.
The GA chip utilization factor is higher when compared to that of FPGA and in terms of speed also it is higher. One of the most custom design styles is Semi-Custom design style. All the used logic cells are developed and characterized and stored in cell library. When we consider the full custom design, the mask design implemented without the usage of the library.
We can conclude that the 2-DWT is used in many applications related to the image compression techniques.
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