VLSI Design Concept for Parallel Iterative Algorithms Project Report

Introduction to VLSI Design Concept for Parallel Iterative Algorithms Project:

Designing an circuit becomes more complicated, especially when the Very Large Scale Integration (VLSI) technology node Keeps shrinking down to Nano scale level. Nano-technology allows integration of number of IP macro-cells on a single chip which leads to the development of Dual-core CPU and parallel computing.

A design of parallel iterative algorithm takes to different VLSI technologies in terms of area, power and timing delay. This paper discuss about the efficient strategy for balancing the number of iterations and the computational complexity. In case of having an hardware platform, which requires an iteration step of an iterative algorithm to execute k times, then this situation can be solved by executing the iterative steps in parallel platform. For this we use 

  • Jacobi method – This method computes the EVD of n×n symmetric matrix iteratively by applying a sequence of orthonormal rotations to the left and the right of the matrix.

Architecture Consideration is necessary to simplify the CORDIC architecture. It is possible to implement a full Jacobi EVC array into a single FPGA device. We could only realize a 6×6 multicore array at most in the biggest Xilinx FPGA device, so we must simplify the CORDIC architecture, the first step is modifying a simplified scaling free μ-rotation CORDIC, this simplified PE has 2 adders, 2 shifters and 4 multiplexers, and it reduces the number of inner iterations from 16 or 32 times for a full CORDIC with word length 16 and 32 bits to 6 inner iterations with CORDIC circular rotation mode. 

Experimental results for an cyclic–by–row parallel Jacobi EVD method in Matlab gives an result of

  • Full rotation CORDIC with 32 iteration steps.
  • Half rotation CORDIC with 16 iteration steps.
  • Simplified μ-rotation CORDIC with one single inner iteration step (μ-CORDIC).
  • Simplified μ-rotation CORDIC with 6 inner iteration

FPGA implementation have a modeled μ-rotation CORDIC PE in VHDL and compared with a full-pipeline CORDIC which is generated, experimental results also show that a 25×25 full Jacobi EVD array can be embedded into Xilinx XC5VL330 65nm FPGA device.

Download VLSI Design Concept for Parallel Iterative Algorithms Project Report

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