Design and Implementation of a Digital To Analog Converter Using VHDL AMS

Design And Implementation Of A  Digital To Analog Converter Using VHDL AMS Project explains about designing a new system through which complex designs can be made easy and feasible. Using these system designers to design model systems quickly and provide best way to simulated chip design and performance at the starting stage of design.

This application will provide users to simulate entire design by dividing each block logically. This process can be continued until final design is finalized. Basically in order to design this type of applications it may take more than few months but by busing this application it can be complemented in weeks which will help companies to reach their dead lines in time.

New analog to digital converter is combined with different digital interfacings and interactions. In old SPCE tools users need to develop different analog and digital sub systems in isolation.

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Implementation of DCT and IDCT Technique on Image Compression Using VHDL

Implementation Of DCT and IDCT Technique On Image Compression Using VHDL Projects main idea is to develop a efficient compression method for images. DCT is a efficient mathematical method which can convert data from amplitude representation to frequency representation. As DCT is one of the mostly used method for filtering, multiplexing , speech coding and image coding. 2D DCT is mostly used in image compression. This is also used in telephone coding schemes.

DCT compression technique will be perfect for image compression because of it energy compaction property. In most of the images energy is concentrated at low and middle frequencies and middle frequency is visible for a normal human eye .

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Design of DDR SDRAM Using Verilog HDL

Design Of DDR SDRAM Using Verilog HDL projects main idea is to find out the problems that are seen in the design and implementation of DDR SDRAM memory controller. This project can be useful as a reference for other applications which are related to DDR SDRAM memory controller. This paper will cover design issues and provide solutions for problems. Information study on this project will also be useful for any design which works on Double Data Rate interface.

DDR Ram is advanced version of basic synchronous DRAM. DDR Ram data transfer rate is fast on each clock cycle which will improve the efficiency by doubling the data output of the memory device.

Other features of DDR Ram are it works as a bidirectional data strobe while data read and data write operations.

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Design And Implementation OF a PLL Using VHDL AMS

Design And Implementation OF a PLL Using VHDL AMS projects main idea is to develop a model for a phase looked Loop in a top down Mixed signal design flow and provide a simulated result for a structural level development and to make a betterment of its behavior.  This project will help us to analyze mixed signals communicating with different digital components in a large circuit is same as that of expected.

In basic circuits time taken for simulating a circuit is more but with this new proposed system simulation time is very less. VHDL-AMS is mostly used for modeling mixed signal circuits. Cadence Analog Artist is used for simulations and schematic level development. This tool will be easily available for users for implementing a new design.

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FPGA Implementation of USB Receiver in HDL

FPGA Implementation of USB Receiver in HDL projects main idea is to develop a receiver application which works for all applications. This receiver is implemented using VHDL USB2.0.

We will test this receiver by downloading it in to FPGA.

In this project Universal Serial Bus version 2.0 is used which works as a bidirectional serial bus interface. Main purpose of using USB 2.0 is because of its three types of UTMI implementations.

USB 2.0 provide high data transmission rates with different speed rates like it works as Low speed(1.5MHZ) for (LS) and works at 12MHZ for Full speed and 480MHZ for High speed data transmission. USB 2.0 consists of transmitter and receiver where UTMI transmitter will send signals to different USB devices on D+ and D- lines and receiver will receive on the same lines.

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Pulse Width Modulated Switching Strategy for the Dynamic Balancing

Pulse Width Modulated Switching Strategy for the dynamic balancing project explains about a new procedure for reducing Zero-sequence current in DC-power supply using pulse width modulation. Using this technique in three level inversion using space vector location can be perfect solution for solving this problem. In pulse width modulation each signal is sample at different time intervals which will improve effectiveness of the process.

This project can be used as final year project for electronics and electrical students. Detailed explanation of the project is explained in the document.

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New Technology for HVDC Start-Up and Operation Using VSC-HVDC System

New Technology For HVDC Start-Up and Operation Using VSC-HVDC System project explains about a new technology which works on low power in the passive network. HVDC is implemented at receiving end of the passive network. The main motive of this application is to reduce power consumption for passive networks.

This application is developed of starting HVDC by VSC-HVDC da reference frame is used for designing a control system. Before designing this application performance of HVDC using VSC-HVDC is calculated. Simulators are designed using PSCAD/EMTDC software package. HVDC can support passive network by feeding small amount of power.

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Possibility of Power Tapping From Composite AC-DC Power Transmission Lines

Possibility of Power Tapping From Composite AC-DC Power Transmission Lines project explains about procedure to handle high voltage ac lines which are loaded with thermal limits. Basically DC currents are carried by conductors with AC super imposed on lines. This paper covers explanation about how rural areas can access power transmission by using simple power tapping procedure.

This can be done by using a PSCAD/EMTDC software package with a digitally simulated scheme. Using simulators a rapid test is conducted to find out how tapping will affect composite AC-DC transmission line and its effect on total power system. Result from simulator shows there is negligible impact on normal AC-DC power lines.

This paper shows how power system can be modified to composite ac-dc line by changing it from existing EHV lines.

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Enhancing the Available Transfer Capability from Source

The main aim of Enhancing The Available Transfer Capability From Source project is to enhance the Available Transfer Capability (ATC) from Generating/Source area to Sink area in a De-regulated environment system location and control parameter of FACTs Devices such as TCSC or SVC on IEEE 14-bus system and IEEE 24 reliability test system.

Real-code Genetic Algorithm is used to determine location and control parameter of TCSC or SVC. ATC is dependent.Hence, maximum use of existing transmission assets will be more profitable for Transmission System Operators (TSO) and customers will receive better services with reduced prices.

Reliability Test System considering without and with line outage cases, and the results are checked. The new system methodology is applied to find best place and control parameter of TCSC/SVC.

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Combined Economic And Emission Dispatch Using Genetic Algorithm & Lambda

Combined Economic And Emission Dispatch Using Genetic Algorithm & Lambda Project explains a solution to solve CEED problem by using Lambda iteration. 

The harmful ecological effects caused by the emission of particulate and gaseous pollutants like sulfur dioxide (SO2 ) and oxides of nitrogen ( NOx ) can be reduced by adequate distribution of load between the plants of a power system. However, this leads to a noticeable increase in the operating cost of the plants. 

In this work, incremental cost is taken as the encoded parameter of GA and PSO, which makes the problem independent of the number of the generator units and also the total count of iterate for convergence reduces fast. 

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