Find the below 2015-2016 IEEE VLSI Projects List for ME/M.Tech Final Year Students. Here Student can select any project Title., Our VLSI Developers has developed projects as per the journal paper. We can provide Abstract, Project Source Code, Documentation, PPT Presentation and Execution Support. Contact us for more details.

We Provide Journal Projects and solutions for B.Tech, M.Tech and Research, We can provide solution for any paper and develop the code with an extension., If you have selected any paper then Feel free to share your idea with us.

V.L.S.I PROJECTS 2016

  1. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
  2. Variable Latency Speculative Han-Carlson Adder
  3. An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes
  4. Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
  5. Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications
  6. Design and Analysis of Approximate Compressors for Multiplication
  7. Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
  8. Low-Power Programmable PRPG with Test Compression Capabilities
  9. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
  10. Recursive Approach to the Design of a Parallel Self-Timed Adder
  11. Efficient Coding Schemes for Fault-Tolerant Parallel Filters
  12. High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations
  13. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
  14. An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability
  15. A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders
  16. Trade-Offs for Threshold Implementations Illustrated on AES
  17. Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks
  18. Reliable and Error Detection Architectures of Pomaranch for False-AlarmSensitive Cryptographic Applications
  19. A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT
  20. Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT
  21. Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes
  22. Advanced Low Power RISC Processor Design using MIPS Instruction Set
  23. Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures

 

 

S.NO

 

PROJECT TITLES

 

IEEE

 

1 High – Throughput Finite Field Multipliers Using Redundant Basis For Fpga And Asic Implementations 2015
2 A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable Orthogonal Approximation Of   Dct 2015
3 Low Delay Single Symbol Error Correction Codes Based On Reed Solomon Codes 2015
4 Fully Reused VLSI Architecture Of Fm0/Manchester Encoding Using Sols Technique For Dsrc Applications 2015
5 Obfuscating Dsp Circuits Via High-Level Transformations 2015
6 Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit Encoding 2015
7 An Efficient Constant Multiplier Architecture Based On Vertical-Horizontal Binary Common Sub-Expression Elimination Algorithm For Reconfigurable Fir Filter Synthesis 2015
8 Flexible Dsp Accelerator Architecture Exploiting Carry-Save Arithmetic 2015
9 Low-Latency High-Throughput Systolic Multipliers Over For Nist Recommended Pentanomials 2015
10 A Synergetic Use Of Bloom Filters For Error Detection And Correction 2015
11 Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block 2015
12 Recursive Approach To The Design Of A Parallel Self-Timed Adder 2015
13 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic 2015
14 Efficient Sub Quadratic Space Complexity Architectures For Parallel Mpb Single- And Double-Multiplications For All Trinomials Using Toeplitz Matrix-Vector Product Decomposition 2015
15 Fine-Grained Critical Path Analysis And Optimization For Area-Time Efficient Realization Of Multiple Constant Multiplications 2015
16 Fast Sign Detection Algorithm For The Rns Moduli Set {2n+1 − 1, 2n − 1, 2n} 2015
17 Algorithm And Architecture For A Low-Power Content-Addressable Memory Based On Sparse Clustered Networks 2015
18 Scan Test Bandwidth Management For Ultralarge-Scale System-On-Chip Architectures 2015
19 Novel Shared Multiplier Scheduling Scheme For Area-Efficient FFT/IFFT Processors 2015
20 VLSI Computational Architectures For The Arithmetic Cosine Transform 2015
21 A Generalization Of Addition Chains And Fast Inversions In Binary Fields 2015
22 Low-Power And Area-Efficient Shift Register Using Pulsed Latches 2015
23 Communication Optimization Of Iterative Sparse Matrix – Vector Multiply On GPUs And FPGAs 2015
24 A Self-Powered High-Efficiency Rectifier With Automatic Resetting Of Transducer Capacitance In Piezoelectric Energy Harvesting Systems 2015
25 Low-Power Programmable PRPG With Test Compression Capabilities 2015
26 One Minimum Only Trellis Decoder For Non – Binary Low – Density Parity – Check Codes 2015
27 A Low Complexity Scaling Method For The Lanczos Kernel In Fixed-Point Arithmetic 2015
28 Mixing Drivers In Clock-Tree For Power Supply Noise Reduction 2015
29 A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter For Sub-mW Energy Harvesting Applications 2015
30 Simplified Trellis Min–Max Decoder Architecture For Nonbinary Low-Density Parity-Check Codes 2015
31 New Regular Radix-8 Scheme For Elliptic Curve Scalar Multiplication Without Pre-Computation 2015
32 Fault Tolerant Parallel Filters Based On Error Correction Codes 2015
33 Comments On “Low-Latency Digit-Serial Systolic Double Basis Multiplier Over GF (2m ) Using Subquadrat Ic Toeplitz Matrix- Vector Product Approach” 2015
34 Skewed-Load Test Cubes Based On Functional Broadside Tests For A Low-Power Test Set 2015
35 Low-Complexity Tree Architecture For Finding The First Two Minima 2015
36 Efficient Coding Schemes For Fault-Tolerant Parallel Filters 2015
37 Piecewise-Functional Broadside Tests Based On Reachable States 2015
38 A Multicycle Test Set Based On A Two-Cycle Test Set With Constant Primary Input Vectors 2015
39 Partially Parallel Encoder Architecture For Long Polar Codes 2015
40 Novel Block-Formulation And Area-Delay – Efficient Reconfigurable Interpolation Filter Architecture Formulti – Standard SDR Applications 2015
41 An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator 2014
42 Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip 2014
43 A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits 2014
44 Fast Radix-10 Multiplication Using Redundant BCD Codes 2014
45 A parallel radix-sort-based VLSI architecture for finding the first W maximum/minimum values 2014
46 Multifunction Residue Architectures for Cryptography 2014
47 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low

Adaptation-Delay

2014
48 32 Bit×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler 2014
49 Recursive Approach to the Design of a Parallel Self-Timed Adder 2014
50 Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications 2014
51 Statistical Analysis of MUX-Based Physical Unclonable Functions 2014
52 Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme 2014
53 Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation 2014
54 Efficient Integer DCT Architectures for HEVC 2014
55 Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm 2014
56 A Method to Extend Orthogonal Latin Square Codes 2014
57 Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter 2014
58 Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator 2014
59 On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays 2014
60 Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata 2014
61 Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding 2014
62 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic 2014
63 Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes 2014
64 Area–Delay–Power Efficient Carry-Select Adder 2014
65 Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences 2014
66 Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement 2014
67 Digitally Controlled Pulse Width Modulator for On-Chip Power Management 2014
68 Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States 2014
69 Area-Delay Efficient Binary Adders in QCA 2014
70 Sharing Logic for Built-In Generation of Functional Broadside Tests 2014