Latest ECE Seminar Topic on A VHDL Primer


This project is to introduce a VHDL language, a hardware description language.  This language is used to model a digital system. VHDL-Very Hard Description Language is a verbose language with many constructs and also very difficult to understand. But the subset of VHDL is simple easy to understand. By using simple set of few features in this language, a reader can start writing models in VHDL. VHDL language has many features especially sequential language part form the ADA programming language.


This language can be used as communication medium between chip vendors and CAD tool users and also between CAD and CAE tools. To describe an entity, VHDL provides 5 design units like entity declaration, architectural body, configuration declaration, package declaration and package body. An entity in VHDL is validated using an analyzer and simulator.

Simulation is a validation process which takes places once the model description is compiled into one or more design libraries.  A simulation can be performed on a configuration or on anentity declaration and an architecture body pair.  Elaboration and Initialization phases are two major steps which need to be carried out before preceding with the actual simulation. Identifiers, data objects, data types, operators are the basic elements of this language. 

Like C or Pascal, an entity behavior is expressed using sequential executed and procedural type code. A dataflow model gives the entity functionality without dealing with its structure. In structural modeling an entity is modeled in a way such that a set of components connected by signals.

In VHDL , compiled design units stored in specific design libraries and package is the term which represents how to store and share declarations that are common for many design units. VHDL describes its own bench models to validate the designed simulation hardware models.  Arbitrarily large designs can model using this language and also not imposing any limitation on the size of a design.  The elements of this language help to make large scale design modeling. 

 Download  Latest ECE Seminar Topic on A VHDL Primer.

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