Introduction to Designing Reduced Instruction Set computer (RISC) Processor Using VHDL Project:
The designing of super-efficient computer processors and accelerators for hardware is done mainly by reducing the control of the compiler hardware to a low level. RISC computing or reduced instruction set computing is a design of the CPU that can provide higher performance by simplified instructions which leads to a faster execution.
RISC is a system that allows the usage of optimized set of instruction to the highest level and uses the load/store architecture. Primitive computer languages were used to analyze the sequential programs, much similarly standard language are used to define the digital circuits. Hardware description language or HDL is used in hardware elements to concurrent the process model in it. The cost effectiveness of the RISC model has impressed many of those who design a compact hardware.
The first step in designing is to test a program to check the input and output in the design module under various conditions. A simulator tool called Verilog simulator verifies the functioning of the design. Algorithm and logical unit will be synthesized and generation of a netlistwill happen which in turn will be transformed into a programmable logic device or PLD image file. The test jig is wired and verified after the PLD files are programmed in a device called CPLD.
Verilog HDL has many pros comparing to the other HDL’s. No special technology is selected while designing, also redesigning the circuit also don’t emerge as a case. The design is implemented into the tool and a gate level net list is created, the verification process is done in the design stage itself eliminating the errors and cons there and then itself.
The functional units of the machine:
Various functions includes data operations on ALU, storage, instruction, address registers and program counter content changing, altering memory content , data retrieval , bus movement controls etc.
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